-
1
-
-
0003510233
-
-
Technical Report 1342, Computer Science Dept., Univ. of Wisconsin-Madison, June
-
D. Burger, T. Austin, and S. Bennett, "Evaluating Future Microprocessors: The Simple Scalar Tool Set," Technical Report 1342, Computer Science Dept., Univ. of Wisconsin-Madison, June 1997.
-
(1997)
Evaluating Future Microprocessors: The Simple Scalar Tool Set
-
-
Burger, D.1
Austin, T.2
Bennett, S.3
-
2
-
-
0026155511
-
Single Instruction Stream Parallelism Is Greater Than Two
-
27-30 May
-
M. Butler, T.-Y. Yeh, Y. Patt, M. Alsup, H. Scales, and M. Shebanow, "Single Instruction Stream Parallelism Is Greater Than Two," Proc. 18th Ann. Int'l Symp. Computer Architecture, pp. 276-286, 27-30 May 1991.
-
(1991)
Proc. 18th Ann. Int'l Symp. Computer Architecture
, pp. 276-286
-
-
Butler, M.1
Yeh, T.-Y.2
Patt, Y.3
Alsup, M.4
Scales, H.5
Shebanow, M.6
-
4
-
-
0029182726
-
Single-Program Speculative Multithreading (SPSM) Architecture: Compiler-Assisted Fine-Grained Multithreading
-
27-29 June
-
PK. Dubey, K. O'Brien, K. O'Brien, and C. Barton, "Single-Program Speculative Multithreading (SPSM) Architecture: Compiler-Assisted Fine-Grained Multithreading," Proc. IFIP WG 10.3 Working Conf. Parallel Architectures and Compilation Techniques, PACT '95, pp. 109-121, 27-29 June 1995
-
(1995)
Proc. IFIP WG 10.3 Working Conf. Parallel Architectures and Compilation Techniques, PACT '95
, pp. 109-121
-
-
Dubey, P.K.1
O'Brien, K.2
O'Brien, K.3
Barton, C.4
-
5
-
-
0029547346
-
The M-Machine Multicomputer
-
Ann Arbor, Mich., Nov.
-
M. Fillo, S.W. Keckler, W.J. Dally, N.P. Carter, A. Chang, Y. Gurevich, and W.S. Lee, "The M-Machine Multicomputer," Proc. 28th Int'l Symp. MicroArchitecture (MICRO), pp. 146-156, Ann Arbor, Mich., Nov. 1995.
-
(1995)
Proc. 28th Int'l Symp. MicroArchitecture (MICRO)
, pp. 146-156
-
-
Fillo, M.1
Keckler, S.W.2
Dally, W.J.3
Carter, N.P.4
Chang, A.5
Gurevich, Y.6
Lee, W.S.7
-
6
-
-
0026865603
-
The Expandable Split Window Paradigm for Exploiting Fine-Grained Parallelism
-
19-21 May
-
M. Franklin and G.S. Sohi, "The Expandable Split Window Paradigm for Exploiting Fine-Grained Parallelism," Proc. 19th Ann. Int'l Symp. Computer Architecture, pp. 58-67, 19-21 May 1992.
-
(1992)
Proc. 19th Ann. Int'l Symp. Computer Architecture
, pp. 58-67
-
-
Franklin, M.1
Sohi, G.S.2
-
7
-
-
0026869325
-
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
-
Gold Coast, Australia, May
-
H. Hirata, K. Kimura, S. Nagamine, Y. Mochizuki, A. Nishimura, Y. Nakase, and T. Nishizawa, "An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads," Proc. 19th Int'l Symp. Computer Architecture (ISCA), pp. 136-145, Gold Coast, Australia, May 1992.
-
(1992)
Proc. 19th Int'l Symp. Computer Architecture (ISCA)
, pp. 136-145
-
-
Hirata, H.1
Kimura, K.2
Nagamine, S.3
Mochizuki, Y.4
Nishimura, A.5
Nakase, Y.6
Nishizawa, T.7
-
8
-
-
0031642920
-
An Efficient Strategy for Developing a Simulator for a Novel Concurrent Multithreaded Processor
-
19-24 July
-
J. Huang and D.J. Lilja, "An Efficient Strategy for Developing a Simulator for a Novel Concurrent Multithreaded Processor," Proc. Sixth Int'l Symp. Modeling, Analysis, and Simulation of Computer and Telecomm. Systems, pp. 185-191, 19-24 July 1998.
-
(1998)
Proc. Sixth Int'l Symp. Modeling, Analysis, and Simulation of Computer and Telecomm. Systems
, pp. 185-191
-
-
Huang, J.1
Lilja, D.J.2
-
11
-
-
84957692552
-
Compiler Techniques for Concurrent Multithreading with Hardware Speculation Support
-
Aug.
-
Z. Li, J.-Y. Tsai, X. Wang, P.-C. Yew, and B. Zheng, "Compiler Techniques for Concurrent Multithreading with Hardware Speculation Support," Proc. Ninth Workshop Languages and Compilers for Parallel Computing, pp. 175-191, Aug. 1996.
-
(1996)
Proc. Ninth Workshop Languages and Compilers for Parallel Computing
, pp. 175-191
-
-
Li, Z.1
Tsai, J.-Y.2
Wang, X.3
Yew, P.-C.4
Zheng, B.5
-
12
-
-
0031234685
-
Trace Processors: Moving to Fourth Generation Microarchitectures
-
Sept.
-
J. Smith and S. Vajapeyam, "Trace Processors: Moving to Fourth Generation Microarchitectures," Computer, vol. 30, no. 9, pp. 68-74, Sept. 1997.
-
(1997)
Computer
, vol.30
, Issue.9
, pp. 68-74
-
-
Smith, J.1
Vajapeyam, S.2
-
13
-
-
0010401153
-
-
Technical Report CSL-TR-91-497, Stanford Univ., Stanford, Calif., Nov.
-
M.D. Smith, "Tracing with Pixie," Technical Report CSL-TR-91-497, Stanford Univ., Stanford, Calif., Nov. 1991.
-
(1991)
Tracing with Pixie
-
-
Smith, M.D.1
-
14
-
-
0029178210
-
Multiscalar Processors
-
22-24 June
-
G.S. Sohi, S.E. Breach, and T.N. Vijaykumar, "Multiscalar Processors," Proc. 22nd Ann. Int'l Symp. Computer Architecture, pp. 414-425, 22-24 June 1995.
-
(1995)
Proc. 22nd Ann. Int'l Symp. Computer Architecture
, pp. 414-425
-
-
Sohi, G.S.1
Breach, S.E.2
Vijaykumar, T.N.3
-
16
-
-
0031611004
-
Performance Study of a Concurrent Multithreaded Processor
-
31 Jan.-4 Feb.
-
J.-Y. Tsai, Z. Jiang, E. Ness, and P.-C. Yew, "Performance Study of a Concurrent Multithreaded Processor," Proc. Fourth Int'l Symp. High Performance Computer Architecture (HPCA-4), pp. 24-33, 31 Jan.-4 Feb. 1998.
-
(1998)
Proc. Fourth Int'l Symp. High Performance Computer Architecture (HPCA-4)
, pp. 24-33
-
-
Tsai, J.-Y.1
Jiang, Z.2
Ness, E.3
Yew, P.-C.4
-
18
-
-
0029727822
-
The Superthreaded Architecture: Thread Pipelining with Run-Time Data Dependence Checking and Control Speculation
-
20-23 Oct.
-
J.-Y. Tsai and P.-C. Yew, "The Superthreaded Architecture: Thread Pipelining with Run-Time Data Dependence Checking and Control Speculation," Proc. 1996 Conf. Parallel Architectures and Compilation Techniques, PACT '96, pp. 35-46, 20-23 Oct. 1996.
-
(1996)
Proc. 1996 Conf. Parallel Architectures and Compilation Techniques, PACT '96
, pp. 35-46
-
-
Tsai, J.-Y.1
Yew, P.-C.2
-
19
-
-
0029200683
-
Simultaneous Multithreading: Maximizing On-Chip Parallelism
-
D.M. Tullsen, S.J. Eggers, and H.M. Levy, "Simultaneous Multithreading: Maximizing On-Chip Parallelism," Proc. 22nd Int'l Symp. Computer Architecture (ISCA), pp. 392-403, 1995.
-
(1995)
Proc. 22nd Int'l Symp. Computer Architecture (ISCA)
, pp. 392-403
-
-
Tullsen, D.M.1
Eggers, S.J.2
Levy, H.M.3
-
21
-
-
0026980844
-
Enhanced Modulo Scheduling for Loops with Conditional Branches
-
1-4 Dec.
-
N.J. Warter, G.E. Haab, J.W. Bockhaus, and K. Subramanian, "Enhanced Modulo Scheduling for Loops with Conditional Branches," Proc. 25th Ann. Int'l Symp. Microarchitecture, pp. 170-179, 1-4 Dec. 1992.
-
(1992)
Proc. 25th Ann. Int'l Symp. Microarchitecture
, pp. 170-179
-
-
Warter, N.J.1
Haab, G.E.2
Bockhaus, J.W.3
Subramanian, K.4
-
23
-
-
0026137273
-
A Variable Instruction Stream Extension to the VLIW Architecture
-
Santa Clara, Calif., Apr.
-
A. Wolfe and J.P. Shen, "A Variable Instruction Stream Extension to the VLIW Architecture," Proc. Fourth Int'l Symp. Architecture Support for Programming Languages and Operating Systems, pp. 2-14, Santa Clara, Calif., Apr. 1991.
-
(1991)
Proc. Fourth Int'l Symp. Architecture Support for Programming Languages and Operating Systems
, pp. 2-14
-
-
Wolfe, A.1
Shen, J.P.2
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