Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 11, 1996, Pages 1424-1434

  Berkelaar, Michel R C M ^a,b   Buurman, Pim H W ^a,b   Jess, Jochen A G ^a,b  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b Xinon BV   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; PIECEWISE LINEAR TECHNIQUES; PROBLEM SOLVING;

ACTIVE AREA/POWER CONSUMPTION; DELAY TRADEOFF CURVE;

LOGIC GATES;

EID: 0030285506     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.543774     Document Type: Article

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