Optimized power-delay curve generation for standard cell ICs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 387-394

  Vujkovic, Miodrag ^a   Sechen, Carl ^a  

^a University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELL LIBRARIES; OPTIMIZED POWER-DELAY CURVE GENERATION; POWER AND PERFORMANCE OPTIMIZATION; TRANSISTOR-LEVEL RESYNTHESIS;

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; FORMAL LOGIC; OPTIMIZATION; PROGRAM COMPILERS; REDUNDANCY;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0036907215     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774630     Document Type: Conference Paper

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