Layout driven data communication optimization for high level synthesis

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Kastner, Ryan ^a   Gong, Wenrui ^a   Hao, Xin ^a   Brewer, Forrest ^a   Kaplan, Adam ^b   Brisk, Philip ^b   Sarrafzadeh, Majid ^b  

^a University of California   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; PERTURBATION TECHNIQUES;

CIRCUIT LAYOUTS; HARDWARE DESCRIPTION; HIGH LEVEL SYNTHESIS; LAYOUT DRIVEN DATA COMMUNICATION;

DATA COMMUNICATION SYSTEMS;

EID: 34047161898     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.244021     Document Type: Conference Paper

References (12)

1. A. Kaplan, P. Brisk, and R. Kastner, "Data communication estimation and reduction for reconfigurable systems," Design Automation Conference, 2003.
2. R. Cytron, J. Ferrante, B. K. Rosen, M. N. Wegman, and F. K. Zadeick, "An efficient method of computing static single assignment form," Symposium on Principles of Programming Languages, 1989.
3. M. Budiu and S. C. Goldstein, "Compiling application-specific hardware," International Conference on Field-Programmable Logic and Application, 2002.
4. J. L. Tripp, P. A. Jackson, and B. L. Hutchings, "Sea cucumber: a synthesizing compiler for FPGAs," International Conference on Field-Programmable Logic and Applications, 2002.
5. W. Gong, G. Wang, and R. Kastner, "A High Performance Intermediate Representation for Reconfigurable Systems," International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004.
6. P. Prabhakaran and P. Banerjee, "Simultaneous scheduling, binding and floorplanning in high-level synthesis," International Conference on VLSI Design, 1997.
7. F. Yung-Ming and D. F. Wong, "Simultaneous functional-unit binding and floorplanning," International Conference on Computer-Aided Design. 1994.
8. W. E. Dougherty and D. E. Thomas, "Unifying behavioral synthesis and physical design," Design Automation Conference, 2000.
9. D. W. Knapp, "Fasolt: a program for feedback-driven data-path optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 11, pp. 677-95, 1992.
10. S. Tarafdar and M. Leeser, "A data-centric approach to high-level synthesis," IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 19, pp. 1251-67,2000.
11. L. Chunho, M. Potkonjak, and W. H. Mangione-Smith, "MediaBench: a tool for evaluating and synthesizing multimedia and communications systems," International Symposium on Microarchitecture, 1997.
12. A. Ranjan, and M. Sarrafzadeh, "Floorplanner 1000 Times Faster: A Good Predictor and Constructor," Workshop on System-Level Interconnection Prediction (SLIP), 1999.