Novel wire density driven full-chip routing for CMP variation control

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 831-838

  Chen, Huang Yu ^a   Chou, Szu Jui ^a   Wang, Sheng Lung ^b   Chang, Yao Wen ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b SYNOPSYS INC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; MASKS; NANOTECHNOLOGY; VLSI CIRCUITS;

COMPUTER-AIDED DESIGN; CRITICAL AREA ANALYSIS; DELAUNAY TRIANGULATION; DENSITY UNIFORMITY; DIELECTRIC THICKNESSES; FULL-CHIP ROUTING; GRID-BASED ROUTING; INTERCONNECT PERFORMANCE; INTERMEDIATE STAGE; INTERNATIONAL CONFERENCES; MASK DATA; NANOMETER TECHNOLOGIES; PLANARITY; PLANARIZATION; SIDE EFFECTS; TOP-DOWN; VORONOI DIAGRAMS;

WIRE;

EID: 50249165989     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397368     Document Type: Conference Paper

References (26)

1. S. N. Adya, S. Chaturvedi, J. A. Roy, D. Papa, and I. L. Markov, "Unification of Partitioning, Floorplanning and Placement," Proc. ICCAD, pp. 550-557, Nov. 2004.
2. S. H. Batterywala, N. Shenoy, W. Nicholls, and H. Zhou, "Track Assignment: A Desirable Intermediate Step Between Global Routing and Detailed Routing," Proc. ICCAD, pp. 59-66, Nov. 2002.
3. Y.-W. Chang and S.-P. Lin, "MR: A New Framework for Multilevel Full-Chip Routing," IEEE TCAD, vol. 23, no. 5, pp. 793-800, May 2004.
4. T.-C. Chen and Y.-W. Chang, "Multilevel Gridless Routing Considering Optical Proximity Correction," Proc. ASP-DAC, pp. 1160-1163, Jan. 2005.
5. T.-C. Chen, Y.-W. Chang, and S.-C. Lin, "A Novel Framework for Multilevel Full-Chip Gridless Routing," Proc. ASP-DAC, pp. 636-641, Jan. 2006.
6. H.-Y. Chen, M.-F. Chiang, Y.-W. Chang, L. Chen, and B. Han, "Novel Full-Chip Gridless Routing Considering Double-Via Insertion," Proc. DAC, pp. 755-760, Jul. 2006.
7. Y. Chen, P. Gupta, and A. B. Kahng, "Performance-Impact Limited Area Fill Synthesis," Proc. DAC, pp. 22-27, Jun. 2003.
8. M. Cho, and D. Z. Pan, "A New Global Router Based on Box Expansion and Progressive ILP," Proc. DAC, pp. 373-378, Jul. 2006.
9. M. Cho, D. Z. Pan, H. Xiang, and R. Puri, "Wire Density Driven Global Routing for CMP Variation and Timing," Proc. ICCAD, pp. 487-492, Nov. 2006.
10. J. D. Cho, S. Raje, and M. Sarrafzadeh, "Approximation for the Maximum Cut, k-Coloring and Maximum Linear Arrangement Problems," Manuscript, Dept. of EECS, Northwestern Univ., 1993.
11. J. Cong, J. Fang, and K. Y Khoo, "DUNE-A Multilayer Gridless Routing System," IEEE TCAD, vol. 20, no. 5, pp. 633-647, May 2001.
12. J. Cong, M. Xie, and Y. Zhang, "An Enhanced Multilevel Routing System," Proc. ICCAD, pp. 51-58, Nov. 2002.
13. M. de Berg, M. van Kreveld, M. Overmars, and O. Schwarzkopf, Computational Geometry: Algorithms and Applications, Springer, 1997.
14. T.-Y. Ho, Y.-W. Chang, S.-J. Chen, and D.-T. Lee, "Crosstalk- and Performance-Driven Multilevel Full-Chip Routing," IEEE TCAD, vol. 24, no. 6, pp. 869-878, Jun. 2005.
15. T.-Y. Ho, C.-F. Chang, Y.-W. Chang, and S.-J. Chen, "Multilevel Full-Chip Routing for the X-Based Architecture," Proc. DAC, pp. 597-602, Jun. 2005.
16. A. B. Kahng, G. Robins, A. Singh, and A. Zelikovsky, "Filling Algorithms and Analyses for Layout Density Control," IEEE TCAD, vol. 18, no. 4, pp. 445-462, Apr. 1999.
17. R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "Pattern Routing: Use and Theory for Increasing Predictability and Avoiding Coupling," IEEE TCAD, pp. 777-790, Nov. 2002.
18. A. Kurokawa, T. Kanamoto, T. Ibe, A. Kasebe, W. F. Chang, T. Kage, Y Inoue, and H. Masuda, "Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills," Proc. ISQED, pp. 586-591, Mar. 2005.
19. K.-S. Leung, "SPIDER: Simultaneous Post-Layout IR-Drop and Metal Density Enhancement with Redundant Fill," Proc. ICCAD, pp. 33-38, Nov. 2005.
20. K. S.-M. Li, Y.-W. Chang, C.-L. Lee, C. Su, and J. E. Chen, "Multilevel Full-Chip Routing with Testability and Yield Enhancement," IEEE TCAD, Sep. 2007.
21. E. Papadopoulou and D. T. Lee, "Critical Area Computation via Voronoi Diagrams," IEEE TCAD, vol. 18, no. 4, pp. 463-474, Apr. 1999.
22. T. H. Park, "Characterization and Modeling of Pattern Dependencies in Copper Interconnects for Integrated Circuits," Ph.D. Dissertation, Dept. of EECS, MIT, May 2002.
23. R. Tian, D. F. Wong, and R. Boone, "Model-Based Dummy Feature Placement for Oxide Chemical-Mechanical Polishing Manufacturability," Proc. DAC, pp. 667-670, Jun. 2000.
24. Taiwan Semiconductor Manufacturing Company (TSMC), Reference Flows 7.0.
25. X. Wang, C. C. Chiang, J. Kawa, and Q. Su, "A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing," Proc. ISQED, pp. 258-263, Mar. 2005.
26. D. White and B. Moore, "An 'Intelligent' Approach to Dummy Fill," EE Times, Jan. 3, 2005.