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Volumn 18, Issue 4, 1999, Pages 445-462

Filling algorithms and analyses for layout density control

Author keywords

Chemical mechanical polishing (cmp); Density control; Layout verification; Manufacturability; Metal fill; Physical design; Yield enhancement

Indexed keywords


EID: 0001130989     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.752928     Document Type: Article
Times cited : (37)

References (30)
  • 6
    • 0001679132 scopus 로고    scopus 로고
    • "Integration of unit processes in a shallow trench isolation module for a 0.25-μ/m complementary metaloxide semiconductor technology," J.
    • A. Chatterjee, I. All, K. Joyner, et al., "Integration of unit processes in a shallow trench isolation module for a 0.25-μ/m complementary metaloxide semiconductor technology," J. Vacuum Sei. Technol. B, vol. 15, pp. 1936-1942, 1997.
    • Vacuum Sei. Technol. B, Vol. 15, Pp. 1936-1942, 1997.
    • Chatterjee, A.1    All, I.2    Joyner, K.3
  • 27
    • 84886448120 scopus 로고    scopus 로고
    • "A simulation methodology for assessing the impact of spatial/pattern dependent interconnect parameter variation on circuit performance," in
    • B. E. Stine, V. Mehrotra, D. S. Boning, J. E. Chung, and D. J. Ciplickas, "A simulation methodology for assessing the impact of spatial/pattern dependent interconnect parameter variation on circuit performance," in IEDM Tech. Dig., pp. 133-136, 1997.
    • IEDM Tech. Dig., Pp. 133-136, 1997.
    • Stine, B.E.1    Mehrotra, V.2    Boning, D.S.3    Chung, J.E.4    Ciplickas, D.J.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.