Critical area computation via voronoi diagrams

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 4, 1999, Pages 463-474

  Papadopoulou, Evanthia ^a,b   Lee, D T ^a,b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b Northwestern University   (United States)

Author keywords

Critical area; Defects; Shorts; Very large scale integration (vlsi) layout; Voronoi diagrams; Yield prediction

Indexed keywords

EID: 33748204187     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.752929     Document Type: Article

References (20)

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