SPIDER: Simultaneous post-layout IR-drop and metal density enhancement with redundant fill

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 33-38

  Leung, Kwok Shing ^a  

^a MAGMA DESIGN AUTOMATION   (United States)

Author keywords

Design for manufacturability; Ground; Metal fill; Power; Voltage drop (IR drop); Yield optimization

Indexed keywords

DESIGN FOR MANUFACTURABILITY; METAL FILL; VOLTAGE DROP (IR-DROP); YIELD OPTIMIZATION;

COMPUTATIONAL METHODS; COMPUTER AIDED DESIGN; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT LAYOUT; ROBUSTNESS (CONTROL SYSTEMS); ROUTERS;

ELECTRIC POWER DISTRIBUTION;

EID: 33751434333     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560036     Document Type: Conference Paper

References (18)

1. I. Ali, S. Roy, and G. Shinn. Chemical mechanical polishing of interlayer dielectric: A review. Solid State Technology, 37(10):63-70, 1994.
2. Y. Chen, A. B. Kahng, G. Robins, and A. Zelikovsky. Area fill synthesis for uniform layout density. IEEE Trans. on Computer-Aided Design, 21(10):1132-1147, 2002.
3. T. H. Cormen, C. E. Leiserson, and R. L. Rivest. Introduction to Algorithm. The MIT Press, Cambridge, Massachusetts, 1993.
4. D. Kouroussis and F. N. Najm. A static pattern-independent technique for power grid voltage integrity verification. In Proc. ACM/IEEE Design Automation Conf., pages 99-104, 2003.
5. T. Mitsuhashi and E. S. Kuh. Power and ground network topology optimization for cell based vlsis. In Proc. ACM/IEEE Design Automation Conf., pages 524-529, 1992.
6. G. Nanz and L. E. Camilletti. Modeling of chemical-mechanical polishing: A review. IEEE Trans. on Semiconductor Manufacturing, 8:382-389, 1995.
7. N. V. Phan and M. J. Rohn. Placement of conductive stripes in electronic circuits to satisfy metal density requirements. United States Patent 6,905,000, 2001.
8. H. Qian, S. R. Nassif, and S. S. Sapatnekar. Earlystage power grid analysis for uncertain working modes. In Proc. ACM/IEEE Int'l. Symp. on Physical Design, pages 132-137, 2004.
9. J. Singh and S. S. Sapetnekar. Topology optimization of structured power/ground networks. In Proc. ACM/IEEE Int'l. Symp. on Physical Design, pages 116-123, 2004.
10. B. E. Stine, D. S. Boning, J. E. Chung, L. Camilletti, F. Kruppa, E. R. Equi, W. Loh, S. Prasad, M. Muthukrishnan, D. Towery, M. Berman, and A. Kapoor. The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes. IEEE Trans. on Electron Devices, 45(3):665-679, 1998.
11. H. Su, K. H. Gala, and S. S. Sapatnekar. Fast analysis and optimization of power/ground networks. In Proc. IEEE/A CM Int'l. Conf. on Computer-Aided Design, pages 477-480, 2000.
12. X. D. S. Tan and C. J. R. Shi. Fast power/ground network optimization based on equivalent circuit modeling. In Proc. ACM/IEEE Design Automation Conf., pages 550-554, 2001.
13. Cadence Design Systems, www.cadence.com.
14. Magma Design Automation, Inc., www.magma-da.com.
15. Mentor Graphics Corp., www.mentor.com.
16. Synopsys Inc., www.synopsys.com.
17. T. Wang and C. C. Chen. Optimization of the power/ground network wire-sizing and spacing based on sequential network simplex algorithm. In Proc. Int'l. Symp. on Quality Electronic Design, pages 157-162, 2002.
18. X. Wu, X. Hong, Y. Cai, C. K. Cheng, J. Gu, and W. Dai. Area minimization of power distribution network using efficient nonlinear programming techniques. In Proc. IEEE/ACM Int'l. Conf. on Computer-Aided Design, pages 153-157, 2001.