-
1
-
-
0003479594
-
Circuits, interconnections, and packaging for VLSI
-
Addison-Wesley, Reading, MA, USA
-
H. B. Bakoglu, Circuits, interconnections, and packaging for VLSI, Addison-Wesley, Reading, MA, USA, 1990.
-
(1990)
-
-
Bakoglu, H.B.1
-
2
-
-
0003945440
-
Algorithms for VLSI physical design automation
-
Kluwer Academic Press
-
N. Sherwani, "Algorithms for VLSI physical design automation," Kluwer Academic Press, 1992.
-
(1992)
-
-
Sherwani, N.1
-
3
-
-
84893735100
-
A sequential detailed router for huge grid graphs
-
A. Hetzel, "A sequential detailed router for huge grid graphs," in Design Automation Conference, 1998, pp. 332-338.
-
Design Automation Conference, 1998
, pp. 332-338
-
-
Hetzel, A.1
-
4
-
-
0035306893
-
Timing and crosstalk-driven area routing
-
Apr.
-
H.-P. Tseng, L. Scheffer, and C. Sechen, "Timing and crosstalk-driven area routing," IEEE Trans. CAD of Integrated Circuits and Systems, vol. 20 no. 4, pp. 528-544, Apr. 2001.
-
(2001)
IEEE Trans. CAD of Integrated Circuits and Systems
, vol.20
, Issue.4
, pp. 528-544
-
-
Tseng, H.-P.1
Scheffer, L.2
Sechen, C.3
-
6
-
-
0024126405
-
Fast algorithm for optimal layer assignment
-
Y. S. Kuo, T. C. Chern, and Wei-Kuan Shih, "Fast algorithm for optimal layer assignment," 25th Design Automation Conference, pp. 554-559, 1988.
-
(1988)
25th Design Automation Conference
, pp. 554-559
-
-
Kuo, Y.S.1
Chern, T.C.2
Wei-Kuan, S.3
-
8
-
-
0032638880
-
An efficient approach to multilayer layer assignment with an application to via minimization
-
May
-
C.-C. Chang and J. Cong, "An efficient approach to multilayer layer assignment with an application to via minimization," IEEE Trans. CAD of Integrated Circuits and Systems, vol. 18, no. 5, pp. 608-620, May 1999.
-
(1999)
IEEE Trans. CAD of Integrated Circuits and Systems
, vol.18
, Issue.5
, pp. 608-620
-
-
Chang, C.-C.1
Cong, J.2
-
10
-
-
0025664148
-
Layer assignment for multichip modules
-
December
-
J. M. Ho, M. Sarrafzadeh, G. Vijayan, and C. K. Wong, "Layer assignment for multichip modules," IEEE Trans. CAD, vol. 9, no. 12, pp. 1272-1277, December 1990.
-
(1990)
IEEE Trans. CAD
, vol.9
, Issue.12
, pp. 1272-1277
-
-
Ho, J.M.1
Sarrafzadeh, M.2
Vijayan, G.3
Wong, C.K.4
-
11
-
-
0024681081
-
Layer assignment for VLSI interconnect delay minimization
-
June
-
M. J. Ciesielski, "Layer assignment for VLSI interconnect delay minimization," IEEE Trans. CAD, vol. 8, no. 6, pp. 701-707, June 1989.
-
(1989)
IEEE Trans. CAD
, vol.8
, Issue.6
, pp. 701-707
-
-
Ciesielski, M.J.1
-
12
-
-
0035306837
-
Optimization of the maximum delay of global interconnects during layer assignment
-
April
-
P. Saxena and C. L. Liu, "Optimization of the maximum delay of global interconnects during layer assignment," IEEE Trans. CAD of Integrated Circuits and Systems, vol. 20, no. 4, pp. 503-515, April 2001.
-
(2001)
IEEE Trans. CAD of Integrated Circuits and Systems
, vol.20
, Issue.4
, pp. 503-515
-
-
Saxena, P.1
Liu, C.L.2
-
13
-
-
0027206842
-
Crosstalk-minimum layer assignment
-
J. D. Cho, S. Raje, M. Sarrafzadeh, M. Siriam, and S. M. Kang, "Crosstalk-minimum layer assignment," Custom Integrated Circuits Conference, pp. 29.7.1-29.7.4, 1993.
-
(1993)
Custom Integrated Circuits Conference
-
-
Cho, J.D.1
Raje, S.2
Sarrafzadeh, M.3
Siriam, M.4
Kang, S.M.5
-
14
-
-
0033692066
-
DUNE: A multi-layer gridless routing system with wire planning
-
J. Cong, J. Fang, and K. Y. Khoo, "DUNE: A multi-layer gridless routing system with wire planning," International Symposium on Physical Design, pp. 12-18, 2000.
-
(2000)
International Symposium on Physical Design
, pp. 12-18
-
-
Cong, J.1
Fang, J.2
Khoo, K.Y.3
-
15
-
-
0033724255
-
Wire packing: A strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution
-
R. Kay and R. A. Rutenbar, "Wire packing: A strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution," International Symposium on Physical Design, pp. 61-68, 2000.
-
(2000)
International Symposium on Physical Design
, pp. 61-68
-
-
Kay, R.1
Rutenbar, R.A.2
-
16
-
-
4243405617
-
Method of designing a constraint-driven integrated circuit layout
-
U.S. Patent number 6,230,304, May
-
P. Groeneveld and L. P. P. P. van Ginneken, "Method of designing a constraint-driven integrated circuit layout," U.S. Patent number 6,230,304, May 2001.
-
(2001)
-
-
Groeneveld, P.1
Van Ginneken, L.P.P.P.2
-
17
-
-
0018547323
-
An optimal solution for the channel assignment problem
-
November
-
U. Gupta, D. T. Lee, and J. Leung, "An optimal solution for the channel assignment problem," IEEE Transactions on Computers, pp. 807-810, November 1979.
-
(1979)
IEEE Transactions on Computers
, pp. 807-810
-
-
Gupta, U.1
Lee, D.T.2
Leung, J.3
-
18
-
-
0001189244
-
The complexity of coloring circular arcs and chords
-
june
-
M. R. Garey, D. S. Johnson, G. L. Miller, and C. H. Papadimitrou, "The complexity of coloring circular arcs and chords," SIAM Journal on Algebraic Discrete Methods, vol. 1, no. 20, pp. 216-227, june 1980.
-
(1980)
SIAM Journal on Algebraic Discrete Methods
, vol.1
, Issue.20
, pp. 216-227
-
-
Garey, M.R.1
Johnson, D.S.2
Miller, G.L.3
Papadimitrou, C.H.4
-
19
-
-
0019923262
-
Efficient algorithms for channel routing
-
January
-
T. Yoshimura and E. S. Kuh, "Efficient algorithms for channel routing," IEEE Trans. CAD of Integrated Circuits and Systems, vol. CAD-1, no. 1, pp. 25-35, January 1982.
-
(1982)
IEEE Trans. CAD of Integrated Circuits and Systems
, vol.CAD-1
, Issue.1
, pp. 25-35
-
-
Yoshimura, T.1
Kuh, E.S.2
-
20
-
-
0003780715
-
-
Addison-Wesley, Reading, MA, USA
-
F. Harary, Graph Theory, Addison-Wesley, Reading, MA, USA, 1972.
-
(1972)
Graph Theory
-
-
Harary, F.1
-
21
-
-
0023173192
-
A shortest augmenting path algorithm for dense and sparse linear assignment problems
-
R. Jonker and A. Volgenant, "A shortest augmenting path algorithm for dense and sparse linear assignment problems," Computing 38, pp. 325-340, 1987.
-
(1987)
Computing
, vol.38
, pp. 325-340
-
-
Jonker, R.1
Volgenant, A.2
-
23
-
-
0012108749
-
Restricted track assignment with applications
-
M. Sarrafzadeh and D. T. Lee, "Restricted track assignment with applications," International Journal of Computational Geometry and Applications, vol. 4, no. 1, pp. 53-68, 1994.
-
(1994)
International Journal of Computational Geometry and Applications
, vol.4
, Issue.1
, pp. 53-68
-
-
Sarrafzadeh, M.1
Lee, D.T.2
|