Signal probability for reliability evaluation of logic circuits

Microelectronics Reliability

Volumn 48, Issue 8-9, 2008, Pages 1586-1591

  Franco, Denis Teixeira ^a,b   Vasconcelos, Maí Correia ^a   Naviner, Lirida ^a   Naviner, Jean François ^a  

^a INSTITUT TELECOM   (France)

^b FEDERAL UNIVERSITY OF RIO GRANDE   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS INDUSTRY; INTEGRATED CIRCUITS; NETWORKS (CIRCUITS); PROBABILITY; QUALITY ASSURANCE; RELIABILITY; RELIABILITY ANALYSIS; RISK ASSESSMENT; SWITCHING CIRCUITS; SWITCHING THEORY;

COMBINATIONAL BLOCKS; DESIGN FLOWS; KEY PARAMETERS; NANOMETER DIMENSIONS; RELIABILITY EVALUATION; SCALE DOWN; SIGNAL PROBABILITY; TRANSIENT FAULTS;

LOGIC CIRCUITS;

EID: 50249118532     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2008.07.002     Document Type: Article

References (21)

1. Shivakumar P, Kistler M, Keckler SW, Burger D, Alvisi L. Modeling the effect of technology trends on the soft error rate of combinational logic. In: Proceedings of international conference on dependable systems and networks, 2002 (DSN 2002), June 2002. p. 389-98.
2. Narayanan V., and Xie Y. Reliability concerns in embedded system designs. Computer 39 1 (2006) 118-120
3. Franco D.T., Naviner J.-F., and Naviner L. Yield and reliability issues in nanoelectronic technologies. Ann Télécommun 61 11-12 (2006) 1422-1457
4. Lala P.K. Self-checking and fault-tolerant digital design (2001), Morgan Kaufmann Publishers, USA
5. Nicolaidis M. Carry checking/parity prediction adders and ALUs. IEEE Trans Very Large Scale Integrat (VLSI) Syst 11 1 (2003) 121-128
6. Lisbôa CA, Schüler E, Carro L. Going beyond TMR for protection against multiple faults. In: Proceedings of the 18th annual symposium on integrated circuits and system design - SBCCI 2005, September 2005. p. 80-5.
7. Mohanram K, Touba N. Cost-effective approach for reducing soft error failure rate in logic circuits. In: Proceedings of international test conference, 2003 (ITC 2003), vol. 1, September 30-October 2, 2003. p. 893-901.
8. Sierawski B.D., Bhuva B.L., and Massengill L.W. Reducing soft error rate in logic circuits through approximate logic functions. IEEE Trans Nucl Sci 53 6 (2006) 3417-3421
9. Zhou Q., and Mohanram K. Gate sizing to radiation harden combinational logic. IEEE Trans Comput-Aid Des Integrat Circuit Syst 25 1 (2006) 155-166
10. Dhillon Y., Diril A., Chatterjee A., and Singh A. Analysis and optimization of nanometer cmos circuits for soft-error tolerance. IEEE Trans Very Large Scale Integrat (VLSI) Syst 14 5 (2006) 514-524
11. Nieuwland A, Jasarevic S, Jerin G. Combinational logic soft error analysis and protection. In: 12th IEEE international on-line testing symposium, 2006 (IOLTS 2006), 10-12 July 2006. p. 6.
12. Ogus R.C. The probability of a correct output from a combinational circuit. IEEE Trans Comput c-24 5 (1975) 534-544
13. Dokouzgiannis S.P., and Kontoleon J.M. Exact reliability analysis of combinational logic circuits. IEEE Trans Reliab 37 5 (1988) 493-500
14. Patel KN, Markov IL, Hayes JP. Evaluating circuit reliability under probabilistic gate-level fault models. In: Proceeding of the twelfth international workshop on logic and synthesis (IWLS 2003), 1 May 2003. p. 59-64.
15. Krishnaswamy S., Viamontes G.F., Markov I.L., and Hayes J.P. Accurate reliability evaluation and enhancement via probabilistic transfer matrices. Proc Des Automat Test Europe (DATE) 1 March (2005) 282-287
16. Bhaduri D, Shukla S, Graham P, Gokhale M. Scalable techniques and tools for reliability analysis of large circuits. In: Proceedings of the 20th international conference on VLSI design, January 2007. p. 705-10.
17. Choudhury MR, Mohanram K. Accurate and scalable reliability analysis of logic circuits. In: Proceedings of design automation and test in Europe (DATE), March 2007. p. 1454-9.
18. Rao R.R., Chopra K., Blaauw D.T., and Sylvester D.M. Computing the soft error rate of a combinational logic circuit using parameterized descriptors. IEEE Trans Comput-Aid Des Integrat Circuit Syst 26 3 (2007) 468-479
19. Ercolani S, Favalli M, Damiani M, Olivo P, Ricco B. Estimate of signal probability in combinational logic networks. In: Proceedings of the 1st European test conference, 12-14 April 1989. p. 132-8.
20. Camurati P, Prinetto P, Reorda M. Random testability analysis: comparing and evaluating existing approaches. In: Proceedings of the IEEE international conference on computer design: VLSI in computers and processors (ICCD '88), 3-5 October 1988. p. 70-3.
21. Vasconcelos MC, Franco DT, Naviner L, Naviner J-F. Reliability analysis of combinational circuits based on a probabilistic binomial model. In: IEEE northest workshop on circuits and systems. NEWCAS-TAISA, 22-25 June; 2008. p. 310-3.