Reliability analysis of combinational circuits based on a probabilistic binomial model

2008 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA

Volumn , Issue , 2008, Pages 310-313

  De Vasconcelos, Maí C R ^a   Franco, Denis T ^a   Naviner, Lirida A De B ^a   Naviner, Jean François ^a  

^a INSTITUT TELECOM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CHLORINE COMPOUNDS; DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC BATTERIES; LOGIC CIRCUITS; NETWORKS (CIRCUITS); PROBABILITY; PROCESS DESIGN; PROCESS ENGINEERING; QUALITY ASSURANCE; RELIABILITY; RELIABILITY ANALYSIS; STANDARDS; SWITCHING CIRCUITS; SWITCHING THEORY;

BINOMIAL MODELS; CIRCUIT STRUCTURES; COMBINATIONAL CIRCUITS; COMBINATIONAL LOGICS; DESIGN PROCESSES; MULTIPLE FAULTS; NANO-SCALE SYSTEMS; PROBABILISTIC MODEL; STANDARD CELLS; SYNTHESIS TOOLS;

ELECTRIC NETWORK ANALYSIS;

EID: 52449091594     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NEWCAS.2008.4606383     Document Type: Conference Paper

References (10)

1. D. T. Franco, J.-F. Naviner, and L. Naviner, "Yield and reliability issues in .nanoelectronics technologies," Annals of Telecommunications, vol. 61, no. 1.1-12, pp. 1247-1282, Dec 2006.
2. ITRS 2006, "International Technology Roadmap for Semiconductors Update," Tech. Rep., 2006.
3. N. Sirisantana, B. C. Paul, and K. Roy, "Enhancing yield at the end of the technology roadmap," IEEE Design and Test of Computers, vol. 21, no. 6, pp. 563-571, nov-dec 2004.
4. K. Nikolic and M. Forshaw, "The relative success of nanoscale RTD, SET and EQCA devices as replacements for CMOS at the system level," Proceedings of the 1st IEEE Conference on Nanotechnology, pp. 272-276, 2001.
5. K. Nikolic, A. Sadek, and M. Forshaw, "Architectures for reliable computing with unreliable nanodevices." Proceedings of the 1st IEEE Conference on Nanotechnology, pp. 254-259, 2001.
6. R. C. Ogus, "The probability of a correct output from a combinatorial circuit," IEEE Transactions on Computers, vol. 24, no. 5, pp. 534-544, may 1975.
7. P. G. Debayan Bhaduri, Sandeep Shukla and M. Gokhale, "Reliability analysis of large circuits using scalable techniques and tools," IEEE Transactions on Circuits and Systems, vol. 54, no. 11, pp. 2447-2460, Nov. 2007.
8. N. Miskov-Zivanov and D. Marculescu, "Circuit reliability analysis using symbolic techniques," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. .12, pp. 2638-2649, dec 2006.
9. R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi, "Algebraic decision diagrams and their applications," Journal of Formal Methods in Systems Design, vol. 10, no. 2-3, pp. 171-206, April-May 1997.
10. S. Krishnaswamy, G. F. Viamontes, I. L. Markov, and J. P. Hayes, "Accurate reliability evaluation and enhancement via probabilistic transfer matrices," Proceedings of Design Automation and Test in Europe, no. 1, pp. 282-287, 2005.