Going beyond TMR for protection against multiple faults

SBCCI 2005 - 18th Symposium on Integrated Circuits and Systems Design

Volumn , Issue , 2005, Pages 80-85

  Lisboa C A L ^a   Schuler E ^b   Carro, Luigi ^b  

^a Instituto de Informática   (Brazil)

^b Depto de Engenharia Elétrica   (Brazil)

Author keywords

Design techniques; Fault tolerance; Future technologies; Simultaneous transient faults

Indexed keywords

ANALOG CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC BREAKDOWN; ERROR CORRECTION; ERRORS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATED CIRCUITS; QUALITY ASSURANCE; RELIABILITY; REUSABILITY; SYSTEMS ANALYSIS;

ANALOG COMPONENTS; ELECTROMAGNETIC NOISES; FAULT TOLERANCE TECHNIQUES; MULTIPLE FAULTS; NEW DESIGN; SOFT ERRORS (SE); SYSTEMS DESIGN;

DIGITAL CIRCUITS;

EID: 34248527474     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2005.4286836     Document Type: Conference Paper

References (19)

1. th Symposium on Integrated Circuits and Systems Design (ICSD 2000), pp. 237-242, IEEE, Manaus, Brazil, September 2000.
2. Anghel, L. and Nicolaidis, M., "Cost Reduction and Evaluation of a Temporary Faults Detection Technique", in Proceedings of Design, Automation and Test in Europe Conference (DATE 2000), pp. 591-598, ACM, Paris, France, March 2000.
3. Beck Fo, A. C. S., Mattos, J. C. B., Wagner, F. R. and Carro, L., "CACO-PS: A General Purpose Cycle-Accurate Configurable Power-Simulator", in Proceedings of the 16th Brazilian Symposium on Integrated Circuits and Systems Design (SBCCI 2003), Sep. 2003.
4. Constantinescu, C., "Trends and Challenges in VLSI Circuit Reliability", IEEE Micro, vol. 23, no. 4, pp. 14-19, IEEE Computer Society, New York-London, July/August 2003.
5. Edenfeld, D.; Kahng, A.B.; Rodgers, M.; Zorian, Y., "2003 Technology Roadmap for Semiconductors", IEEE Computer, vol. 37, pp. 47-56, IEEE Computer Society, New York-London, January 2004.
6. Gupta, S. K., Breuer, M. A. and Mak, T. M., "Defect and Error Tolerance in the Presence of Massive Numbers of Defects", IEEE Design & Test of Computers, vol. 21, issue 3, pp. 216-227, IEEE Computer Society, New York-London, May 2004.
7. Johnson, B.W., Design and Analysis of Fault-Tolerant Digital Systems. Reading, MA: Addison-Wesley Publishing Company 1989.
8. Lima, F., Carro, L. and Reis, R., "Techniques for Reconfigurable Logic Applications: Designing Fault Tolerant Systems into SRAM-based FPGAs", in Proceedings of the International Design Automation Conference, DAC 2003, pp. 650-655, ACM, New York, 2003.
9. Lisboa, C. and Carro, L., "An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets ", in Proceedings of the 10th IEEE International Online Test Symposium -IOLTS 2004, pp. 180, IEEE Computer Society, New York, July 2004.
10. Lisbôa, C. and Carro, L., "Arithmetic Operators Robust to Multiple Simultaneous Upsets", in Proceedings of the 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - DFT 2004, pp. 289-297, ISBN 0-7695-2241-6. IEEE Computer Society, New York, October 2004.
11. Lisbôa, C. and Carro, L., "Highly Reliable Arithmetic Multipliers for Future Technologies", in Proceedings of the International Workshop on Dependable Embedded Systems -WDES 2004 - in conjunction with the 23rd International Symposium on Reliable Distributed Systems - SRDS 2004, pp. 13-18. Edited by Becker, L. B. and Kaiser, J., Florianópolis, October 17,2004.
12. Messenger, G. C., "A Summary Review of Displacement Damage from High Energy Radiation in Silicon Semiconductors and Semiconductor Devices", IEEE Transactions on Nuclear Science, vol. 39, no. 3, pp. 468-473, IEEE Computer Society, New York-London, June 1992.
13. Pflanz, M. and Vierhaus, H. T., "Online Check and Recovery Techniques for Dependable Embedded Processors", IEEE Micro, vol. 21, number 5, pp. 24-40, IEEE Computer Society, New York-London, September-October 2001.
14. Schmid, A. and Leblebici, Y., "A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies", in Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance - DFT 2004, pp. 39-47, ISBN 0-7695-2241-6. IEEE Computer Society, New York, October 2004.
15. Semiconductor Industry Association. International Technology Roadmap for Semiconductors - ITRS 2003, last access November 12,2004. http://public.itrs. net/Files/2003ITRS/Home2003.htm.
16. M. Rebaudengo, M. Sonza Reorda, M. Violante, B. Nicolescu, R. Velazco, "Coping With SEUs/SETs in Microprocessors by means of Low-Cost Solutions: A Comparative Study", IEEE Transactions on Nuclear Science, vol. 49, no. 3, pp. 1491-1495, IEEE Computer Society, New York-London, June 2002.
17. Townsend, W. J., Abraham, J. A. and Lala, P. K., "Online Error Detecting Constant Delay Adder", in Proceedings of the 9th IEEE International Online Testing Symposium, pp. 17-22, Kos Island, Greece, July 7-9, 2003.
18. Wirth, G., Vieira, M. and Kastensmidt, F. L., "Computer Efficient Modeling of SRAM Cells Sensitivity to SEU", in Proceedings of the 6th IEEE Latin America Test Workshop, pp. 51-56, Salvador, Bahia, Brazil, March 30-April 2nd, 2005.
19. Yang, F. L. and Saleh, R. A., "Simulation and Analysis of Transient Faults in Digital Circuits", IEEE Journal of Solid-State Circuits, vol. 27, no. 3, pp. 258-264, IEEE Computer Society, New York-London, March 1992.