Reducing soft error rate in logic circuits through approximate logic functions

IEEE Transactions on Nuclear Science

Volumn 53, Issue 6, 2006, Pages 3417-3421

  Sierawski, Brian D ^a,b   Bhuva, Bharat L ^a,c   Massengill, Lloyd W ^a,c  

^a IEEE   (United States)

^b VANDERBILT UNIVERSITY   (United States)

^c VANDERBILT UNIVERSITY   (United States)

Author keywords

Integrated circuit radiation effects; Logic design; Logical masking; Single event upsets; Soft error rate

Indexed keywords

BENCHMARK CIRCUITS; INTEGRATED CIRCUIT RADIATION EFFECTS; LOGIC FUNCTIONS; LOGICAL MASKING; SINGLE-EVENT UPSETS; SOFT ERROR RATE;

BIT ERROR RATE; INTEGRATED CIRCUITS; LOGIC DESIGN; RADIATION EFFECTS;

LOGIC CIRCUITS;

EID: 33846327558     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2006.884352     Document Type: Conference Paper

References (11)

1. R. C. Baumann, "Radiation-induced soft errors in advanced semiconductor technologies," IEEE Trans. Device Mater. Reliab., vol. 5, no. 3, pp. 305-316, 2005.
2. S. Buchner and M. Baze, "Single-event transients in fast electronic circuits," in Proc. IEEE Nucl. Space Radiation Effects Conf. Short Course Text, 2001.
3. M. Casey, B. Bhuva, J. Black, and L. Massengill, "HBD using cascode-voltage switch logic gates for SEU tolerant digital designs," presented at the IEEE Nucl. and Space Radiation Effects Conf., Seattle, WA, 2005.
4. C. Chen and M. Msiao, "Error-correcting codes for semiconductor memory applications: A state-of-the-art review," IBM J. Res. Develop., vol. 28, pp. 124-134, Mar. 1984.
5. T. Karnik, P. Hazucha, and J. Patel, "Characterization of soft errors caused by single event upsets in cmos processes," IEEE Trans. Dependable Secure Comput., vol. 1, no. 2, pp. 128-143, Apr. 2004.
6. D. G. Mavis and P. H. Eaton, "Soft error rate mitigation techniques for modern microcircuits," in Proc. 40th Reliability Physics Symp., 2002, pp. 216-225.
7. S. Mitra, T. Karnik, N. Seifert, and M. Zhang, "Logic soft errors in sub-65 nm technologies: Design and cad challenges," in Proc. Design Automation Conf., 2005.
8. K. Mohanram and N. Touba, "Partial error masking to reduce soft error failure rate in logic circuits," in Proc. 18th IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, 2003.
9. K. Ravi, K. L. McMillan, T. R. Shiple, and F. Somenzi, "Approximation and decomposition of binary decision diagrams," in Proc. Design Automation Conf., 1998, pp. 445-450.
10. P. Shivakumar, M. Kistler, S. Keckler, D. Burger, and L. Alvisi, "Modeling the effect of technology trends on the soft error rate of combinational logic," in Proc. Int. Conf. Dependable Systems Networks, 2002, pp. 389-398.
11. F. Somenzi, CUDD: CU Decision Diagram Package, Univ. of Colorado. Boulder [Online]. Available: ftp://vlsi.colorado.edu/pub/