Statistical corner conditions of interconnect delay (corner LPE specifications)

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 706-711

  Yamada, Kenta ^a   Oda, Noriaki ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LSI CIRCUITS; SPECIFICATIONS; STATISTICAL METHODS;

INTERCONNECT DELAYS; INTERCONNECT LAYERS; STATISTICAL CORNER CONDITIONS;

INTERCONNECTION NETWORKS;

EID: 33748616504     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118465     Document Type: Conference Paper

References (4)

1. S. Takahashi, Tech. Dig. IEDM, 1998, p.833-836
2. K. Yamada, VLSI Tech. Dig., 2003, p. 111-112
3. S. Inoue, Japanese patent pending, No. P2001-265826A
4. A. Kuroda, Workshop on Circuits and Systems in Karuizawa, 2005, p.25-30