An IC manufacturing yield model considering intra-die variations

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 749-754

  Luo, Jianfeng ^a   Sinha, Subarna ^a   Su, Qing ^a   Kawa, Jamil ^a   Chiang, Charles ^a  

^a SYNOPSYS INC   (United States)

Author keywords

CMP; Manufacturing yield; Random variation; Spatial correlation; Systematic variation

Indexed keywords

CHEMICAL MECHANICAL POLISHING; MODEL CHECKING; NANOLITHOGRAPHY; RANDOM PROCESSES; SPECIFICATIONS;

MANUFACTURING YIELD; RANDOM VARIATION; SPATIAL CORRELATION; SYSTEMATIC VARIATION;

INTEGRATED CIRCUIT MANUFACTURE;

ELECTRIC CIRCUITS; LITHOGRAPHY; MANUFACTURE;

EID: 34347224489     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147100     Document Type: Conference Paper

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