Circuit impact and skew-corner analysis of stochastic process variation in global interconnect

Proceedings of the IEEE 1999 International Interconnect Technology Conference, IITC 1999

Volumn , Issue , 1999, Pages 230-232

  Nakagawa, O S ^a   Chang, N ^a   Lin, S ^a   Sylvester, D ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; DELAY CIRCUITS; INTEGRATED CIRCUIT INTERCONNECTS; INTELLIGENT SYSTEMS; MONTE CARLO METHODS; RANDOM PROCESSES; SPICE; STOCHASTIC SYSTEMS; TIMING CIRCUITS;

CIRCUIT PERFORMANCE; CIRCUIT SIMULATORS; DIELECTRIC THICKNESS; GLOBAL INTERCONNECTS; JOINT PROBABILITY; MANUFACTURING LINES; RESPONSE SURFACE FUNCTIONS; STANDARD DEVIATION;

ELECTRIC NETWORK ANALYSIS;

EID: 85013620407     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.1999.787130     Document Type: Conference Paper

References (3)

1. O. Sam Nakagawa and S.-Y. Oh, Conf. Proceedings of Solid-State Devices and Materials, p. 280, Hamamatsu, Japan, September 1997.
2. D. Sylvester, C. Hu, O. S. Nakagawa, and S.-Y. Oh, VLSI Technology Symposium Digest of Technical Papers, p. 42, Honolulu, HI, June 1998.
3. O. Sam Nakagawa, S.-Y. Oh, and G. Ray, IEDM Tech. Digest, p. 137, Washington, D.C., December 1997