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Volumn , Issue , 2006, Pages

3D nano wire-based programmable logic

Author keywords

[No Author keywords available]

Indexed keywords

COMPACT LAYOUT; FUNDAMENTAL LIMITS; HIGH-QUALITY; INTERNATIONAL CONFERENCES; LOGIC DENSITIES; LOGIC STRUCTURES; MULTIPLE LAYERS; NANO-NET; NANO-NETWORKS; NATURAL PATHS; PROGRAMMABLE LOGICS; SEMICONDUCTING MATERIALS; SEMICONDUCTING NANOWIRES; SURFACE AREA; THREE DIMENSIONS; THREE-DIMENSIONAL SYSTEMS; VERTICAL LAYERS;

EID: 50149097119     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANONET.2006.346223     Document Type: Conference Paper
Times cited : (10)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.