-
1
-
-
0038645356
-
512Mb PROM with 8 layers of antifue/diode cells
-
M. Crowley, A. Al-Shamma, D. Bosch, M. Farmwald, L. Fasoli, A. Ilkbahar, M. Johnson, B. Kleveland, T. Lee, T. yi Liu, Q. Nguyen, R. Scheuerlein, K. So, and T. Throp, "512Mb PROM with 8 layers of antifue/diode cells," in ISSCC, 2003, p. 284.
-
(2003)
ISSCC
, pp. 284
-
-
Crowley, M.1
Al-Shamma, A.2
Bosch, D.3
Farmwald, M.4
Fasoli, L.5
Ilkbahar, A.6
Johnson, M.7
Kleveland, B.8
Lee, T.9
yi Liu, T.10
Nguyen, Q.11
Scheuerlein, R.12
So, K.13
Throp, T.14
-
2
-
-
84948471389
-
Fabrication technologies for three-dimensional integrated circuits
-
R. Reif, A. Fan, K.-N. Chen, and S. Das, "Fabrication technologies for three-dimensional integrated circuits," in ISQED, 2002, pp. 33-37.
-
(2002)
ISQED
, pp. 33-37
-
-
Reif, R.1
Fan, A.2
Chen, K.-N.3
Das, S.4
-
3
-
-
0037619039
-
Preparation of gold, platinum, palladium and silver nanoparticles by the reduction of their salts with a weak reductant-potassium bitartrate
-
Y. Tan, X. Dai, Y. Li, and D. Zhu, "Preparation of gold, platinum, palladium and silver nanoparticles by the reduction of their salts with a weak reductant-potassium bitartrate," J. Mat. Chem., vol. 13, pp. 1069-1075, 2003.
-
(2003)
J. Mat. Chem
, vol.13
, pp. 1069-1075
-
-
Tan, Y.1
Dai, X.2
Li, Y.3
Zhu, D.4
-
4
-
-
0032498174
-
A laser ablation method for synthesis of crystalline semiconductor nanowires
-
A. M. Morales and C. M. Lieber, "A laser ablation method for synthesis of crystalline semiconductor nanowires," Science, vol. 279, pp. 208-211, 1998.
-
(1998)
Science
, vol.279
, pp. 208-211
-
-
Morales, A.M.1
Lieber, C.M.2
-
5
-
-
0035831837
-
Diameter-controlled synthesis of single crystal silicon nanowires
-
Y. Cui, L. J. Lauhon, M. S. Gudiksen, J. Wang, and C. M. Lieber, "Diameter-controlled synthesis of single crystal silicon nanowires," Appl. Phys. Let., vol. 78, no. 15, pp. 2214-2216, 2001.
-
(2001)
Appl. Phys. Let
, vol.78
, Issue.15
, pp. 2214-2216
-
-
Cui, Y.1
Lauhon, L.J.2
Gudiksen, M.S.3
Wang, J.4
Lieber, C.M.5
-
6
-
-
23144452032
-
General syntehsis of manganese-doped II-VI and III-V semiconductor nanowires
-
P. V. Radovanovic, C. J. Barrelet, S. Gradecak, F. Qian, and C. M. Lieber, "General syntehsis of manganese-doped II-VI and III-V semiconductor nanowires," Nanoletters, vol. 5, no. 7, pp. 1407-1411, 2005.
-
(2005)
Nanoletters
, vol.5
, Issue.7
, pp. 1407-1411
-
-
Radovanovic, P.V.1
Barrelet, C.J.2
Gradecak, S.3
Qian, F.4
Lieber, C.M.5
-
7
-
-
0141757466
-
Synthesis of CdS and ZnS nanowires using single-source molecular precursors
-
C. J. Barrelet, Y. Wu, D. C. Bell, and C. M. Lieber, "Synthesis of CdS and ZnS nanowires using single-source molecular precursors," J. Am. Chem. Soc., vol. 125, no. 38, pp. 11498-11499, 2003.
-
(2003)
J. Am. Chem. Soc
, vol.125
, Issue.38
, pp. 11498-11499
-
-
Barrelet, C.J.1
Wu, Y.2
Bell, D.C.3
Lieber, C.M.4
-
8
-
-
15844375538
-
Structures and electrical properties for ag-tetracyanoquinodimetheane organometallic nanowires
-
March
-
Z. Fan, X. Mo, C. Lou, Y. Yao, D. Wang, G. Chen, and J. G. Lu, "Structures and electrical properties for ag-tetracyanoquinodimetheane organometallic nanowires," IEEE Trans. Nanotechnol., vol. 4, no. 2, pp. 238-241, March 2005.
-
(2005)
IEEE Trans. Nanotechnol
, vol.4
, Issue.2
, pp. 238-241
-
-
Fan, Z.1
Mo, X.2
Lou, C.3
Yao, Y.4
Wang, D.5
Chen, G.6
Lu, J.G.7
-
9
-
-
0038161696
-
High Performance Silicon Nanowire Field Effect Transistors
-
Y. Cui, Z. Zhong, D. Wang, W. U. Wang, and C. M. Lieber, "High Performance Silicon Nanowire Field Effect Transistors," Nanoletters, vol. 3, no. 2, pp. 149-152, 2003.
-
(2003)
Nanoletters
, vol.3
, Issue.2
, pp. 149-152
-
-
Cui, Y.1
Zhong, Z.2
Wang, D.3
Wang, W.U.4
Lieber, C.M.5
-
10
-
-
0033737136
-
Doping and electrical transport in silicon nanowires
-
June 8
-
Y. Cui, X. Duan, J. Hu, and C. M. Lieber, "Doping and electrical transport in silicon nanowires," J. of Phys. Chem. B, vol. 104, no. 22, pp. 5213-5216, June 8 2000.
-
(2000)
J. of Phys. Chem. B
, vol.104
, Issue.22
, pp. 5213-5216
-
-
Cui, Y.1
Duan, X.2
Hu, J.3
Lieber, C.M.4
-
11
-
-
0035834415
-
Logic gates and computation from assembled nanowire building blocks
-
November 9
-
Y Huang, X. Duan, Y. Cui, L. Lauhon, K. Kim, and C. M. Lieber, "Logic gates and computation from assembled nanowire building blocks," Science, vol. 294, pp. 1313-1317, November 9 2001.
-
(2001)
Science
, vol.294
, pp. 1313-1317
-
-
Huang, Y.1
Duan, X.2
Cui, Y.3
Lauhon, L.4
Kim, K.5
Lieber, C.M.6
-
12
-
-
0037033988
-
-
M. S. Gudiksen, L. J. Lauhon, J. Wang, D. C. Smith, and C. M. Lieber, Growth of nanowire superlattice structures for nanoscale photonics and electronics, Nature, 415, pp. 617-620. February 7 2002.
-
M. S. Gudiksen, L. J. Lauhon, J. Wang, D. C. Smith, and C. M. Lieber, "Growth of nanowire superlattice structures for nanoscale photonics and electronics," Nature, vol. 415, pp. 617-620. February 7 2002.
-
-
-
-
13
-
-
0037038368
-
Epitaxial core-shell and core-multi-shell nanowire heterostructures
-
L. J. Lauhon, M. S. Gudiksen, D. Wang, and C. M. Lieber, "Epitaxial core-shell and core-multi-shell nanowire heterostructures," Nature, vol. 420, pp. 57-61, 2002.
-
(2002)
Nature
, vol.420
, pp. 57-61
-
-
Lauhon, L.J.1
Gudiksen, M.S.2
Wang, D.3
Lieber, C.M.4
-
14
-
-
0141518628
-
Nanolithography using hierarchically assembled nanowire masks
-
July 9
-
D. Whang, S. Jin, and C. M. Lieber, "Nanolithography using hierarchically assembled nanowire masks," Nanoletters, vol. 3, no. 7, pp. 951-954, July 9 2003.
-
(2003)
Nanoletters
, vol.3
, Issue.7
, pp. 951-954
-
-
Whang, D.1
Jin, S.2
Lieber, C.M.3
-
15
-
-
0034824859
-
Directed assembly of one-dimensional nanostructures into functional networks
-
January 26
-
Y. Huang, X. Duan, Q. Wei, and C. M. Lieber, "Directed assembly of one-dimensional nanostructures into functional networks," Science, vol. 291, pp. 630-633, January 26 2001.
-
(2001)
Science
, vol.291
, pp. 630-633
-
-
Huang, Y.1
Duan, X.2
Wei, Q.3
Lieber, C.M.4
-
16
-
-
0141510585
-
Large-scale hierarchical organization of nanowire arrays for integrated nanosystems
-
September
-
D. Whang, S. Jin, Y. Wu, and C. M. Lieber, "Large-scale hierarchical organization of nanowire arrays for integrated nanosystems," Nanoletters, vol. 3, no. 9, pp. 1255-1259, September 2003.
-
(2003)
Nanoletters
, vol.3
, Issue.9
, pp. 1255-1259
-
-
Whang, D.1
Jin, S.2
Wu, Y.3
Lieber, C.M.4
-
17
-
-
2442424176
-
Nanowire-Based Sublithographic Programmable Logic Arrays
-
February
-
A. DeHon and M. J. Wilson, "Nanowire-Based Sublithographic Programmable Logic Arrays," in FPGA, February 2004, pp. 123-132.
-
(2004)
FPGA
, pp. 123-132
-
-
DeHon, A.1
Wilson, M.J.2
-
18
-
-
85015357431
-
Nanowire-Based Programmable Architectures
-
A. DeHon, "Nanowire-Based Programmable Architectures," ACM J. Emerg. Technol. Comput. Syst., vol. 1, no. 2, pp. 109-162, 2005.
-
(2005)
ACM J. Emerg. Technol. Comput. Syst
, vol.1
, Issue.2
, pp. 109-162
-
-
DeHon, A.1
-
19
-
-
2442617450
-
Stochastic Assembly of Sublitho-graphic Nanoscale Interfaces
-
A. DeHon, P. Lincoln, and J. Savage, "Stochastic Assembly of Sublitho-graphic Nanoscale Interfaces," IEEE Trans. Nanotechnol., vol. 2, no. 3, pp. 165-174, 2003.
-
(2003)
IEEE Trans. Nanotechnol
, vol.2
, Issue.3
, pp. 165-174
-
-
DeHon, A.1
Lincoln, P.2
Savage, J.3
-
20
-
-
50149098943
-
-
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni- Vincentelli, SIS: A system for sequential circuit synthesis, University of California, Berkeley, UCB/ERL M92/41, May 1992.
-
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni- Vincentelli, "SIS: A system for sequential circuit synthesis," University of California, Berkeley, UCB/ERL M92/41, May 1992.
-
-
-
-
21
-
-
0142118131
-
Performance-driven mapping for CPLD architectures
-
October
-
D. Chen, J. Cong, M. Ercegovac, and Z. Huang, "Performance-driven mapping for CPLD architectures," IEEE Trans. Computer-Aided Design, vol. 22, no. 10, pp. 1424-1431, October 2003.
-
(2003)
IEEE Trans. Computer-Aided Design
, vol.22
, Issue.10
, pp. 1424-1431
-
-
Chen, D.1
Cong, J.2
Ercegovac, M.3
Huang, Z.4
-
22
-
-
84957870821
-
-
V. Betz and J. Rose, VPR: A new packing, placement, and routing tool for FPGA research, in FPL, ser. LNCS, W. Luk, P. Y. K. Cheung, and M. Glesner, Eds., no. 1304. Springer, August 1997, pp. 213-222.
-
V. Betz and J. Rose, "VPR: A new packing, placement, and routing tool for FPGA research," in FPL, ser. LNCS, W. Luk, P. Y. K. Cheung, and M. Glesner, Eds., no. 1304. Springer, August 1997, pp. 213-222.
-
-
-
-
23
-
-
50149120092
-
-
June 2004
-
C. Ababei, H. Mogal, P. Maidee, and K. Bazargan, "TPR: Three-dimensional place and route for 3D FPGAs," 〈http://mountains. ece.umn.edu/~kia/Download/tpr.html〉, June 2004.
-
TPR: Three-dimensional place and route for 3D FPGAs
-
-
Ababei, C.1
Mogal, H.2
Maidee, P.3
Bazargan, K.4
-
24
-
-
28344432776
-
-
C. Ababei, Y. Feng, B. Goplen, H. Mogal, T. Zhang, and K. B. ad Sachin Sapatnekar, Placement and routing in 3D integrated circuits, IEEE Des. Test. Comput., 22, no. 6, pp. 520-531, November-December 2005.
-
C. Ababei, Y. Feng, B. Goplen, H. Mogal, T. Zhang, and K. B. ad Sachin Sapatnekar, "Placement and routing in 3D integrated circuits," IEEE Des. Test. Comput., vol. 22, no. 6, pp. 520-531, November-December 2005.
-
-
-
|