Multi-clock driven system: A novel VLSI architecture

International Conference on ASIC, Proceedings

Volumn , Issue , 2001, Pages 555-558

  Dong, Peiliang ^a   Yu, Rilong ^a   Xu, Hongbo ^a   Yu, Chengfang ^a  

^a FUDAN UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; COMBINATORIAL CIRCUITS; DIGITAL CONTROL SYSTEMS; INTEGRATED CIRCUIT LAYOUT; SPURIOUS SIGNAL NOISE; SYSTEMS ANALYSIS;

CLOCK GENERATOR; CLOCK SIGNALS; POWER DISSIPATION;

VLSI CIRCUITS;

EID: 0035721072     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (4)

1. Asynchronous design methodologies: An overview
2. A method for the construction of minimum-redundancy codes