Miller and noise effects in a synchronizing flip-flop

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 6, 1999, Pages 849-855

  Dike, Charles ^a,b,c,d   Burton, Edward ^a,b  

^a INTEL CORPORATION   (United States)

^b BRIGHAM YOUNG UNIVERSITY   (United States)

^c Philips Signetics Company   (United States)

^d Strategic CAD Labs Group   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; STABILITY; SYNCHRONIZATION; THERMAL NOISE;

METASTABILITY; MILLER COUPLING;

FLIP FLOP CIRCUITS;

EID: 0032662748     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.766819     Document Type: Article

References (5)

1. S. T. Flannagan, "Synchronization reliability in CMOS technology," IEEE. J. Solid-State Circuits, vol. SC-20, pp. 880-882, Aug. 1985.
2. L. Kim and R. W. Dutton, "Metastability of CMOS latch/flip-flop," IEEE. J. Solid-State Circuits, vol. 25, pp. 942-950, Aug. 1990.
3. J. G. Jex and C. E. Dike, "A fast resolving BiNMOS synchronizer for parallel processor interconnect," IEEE J. Solid State Circuits, vol. 30, pp. 133-139. Feb. 1995.
4. S. M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1981.
5. A. Van der Ziel, Noise in Measurements. New York: Wiley, 1976.