Quantified impacts of guardband reduction on design process outcomes

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Volumn , Issue , 2008, Pages 790-797

  Jeong, Kwangok ^a   Kahng, Andrew B ^a   Samadi, Kambiz ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA REDUCTION; COMPETITIVE PRESSURE; DESIGN CYCLE-TIME; DESIGN PRACTICES; DESIGN PROCESSES; DESIGN QUALITY; ECONOMIC INCENTIVES; ECONOMIC VIABILITY; ELECTRONIC DESIGNS; EXPERIMENTAL DATA; GUARD BANDS; INTERNATIONAL SYMPOSIUM; OPEN SOURCES; PLACE AND ROUTE; PROCESS VARIATIONS; REDUCED MODELS; SEMICONDUCTOR INDUSTRIES; STANDARD CELLS; TECHNOLOGY ROADMAP; WIRE LENGTHS;

ELECTRONICS ENGINEERING; INDUSTRIAL MANAGEMENT; MILITARY OPERATIONS; PROCESS ENGINEERING; PRODUCT DESIGN; SEMICONDUCTOR DEVICE MANUFACTURE; STANDARDS; TECHNOLOGY; TURNAROUND TIME;

PROCESS DESIGN;

EID: 49749121156     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2008.4479839     Document Type: Conference Paper

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