Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1996, Pages 368-373

  Heineken, Hans T ^a   Maly, Wojciech ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; OPTIMIZATION; SEMICONDUCTOR DEVICE MODELS;

TECHNOLOGY MAPPING OPTIMIZATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0030400099     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)