Impact of subwavelength CD tolerance on device performance

Proceedings of SPIE-The International Society for Optical Engineering

Volumn 4692, Issue , 2002, Pages 361-368

  Balasinski, A ^a   Karklin, L ^b   Axelrad, V ^c  

^a CYPRESS SEMICONDUCTOR   (United States)

^b SYNOPSYS INC   (United States)

^c SEQUOIA Design Systems   (United States)

Author keywords

Endcaps; Optical and electrical simulation; Shrinkability; Silicon image; SRAM layouts

Indexed keywords

FITS AND TOLERANCES; MOSFET DEVICES; PHASE SHIFT; PHOTOLITHOGRAPHY; STATIC RANDOM ACCESS STORAGE;

RESOLUTION ENHANCEMENT TECHNIQUES (RET);

INTEGRATED CIRCUIT LAYOUT;

EID: 0036030215     PISSN: 0277786X     EISSN: None     Source Type: Journal    
DOI: 10.1117/12.475673     Document Type: Article

References (15)

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2. Y. Takao, et al., "A 0.11 um CMOS Technology with Copper and Very-low-k Interconnects for High-Performance System-On-a-Chip Cores," Proc. IEDM, 2000, pp. 559-562.
3. K.K. Young, et al., "A 0.13 um CMOS Technology with 193 nm Lithography and Cu/Low-k for High Performance Applications," Proc. IEDM, 2000, pp. 563-566.
4. S. Tyagi, et al., "A 130 nm generation Logic Technology Featuring 70 nm Transistors, Dual Vt Transistors and 6 Layers of Cu Interconnects," Proc. IEDM, 2000, pp. 567-570.
5. A.H. Perera, et al., "A versatile 0.13 um CMOS Platform Technology supporting High Performance and Low Power Applications," Proc. IEDM, 2000, pp. 571-574.
6. J.H. Jang, H.S. Kim, H.C. Baek, J.J. Na, K.H. Lee, D.S. Seo, K.J. Kim, Y.S. Shin, and C.G. Hwang, "A 2.05 um2 Full CMOS Ultra-Low Power SRAM Cell with 0.15 um Generation Single Gate CMOS Technology," Proc. IEDM, 2000, pp. 579-582.
7. A. Balasinski, "Optimizing the Cost of Design Rule Modifications for Subsequent Generations of Semiconductor Technology," Proc. ASMC 2000, pp. 256-262. Also: Patent pending.
8. A. Balasinski, H. Gangala, V. Axelrad, and V. Boksha, "A Novel Approach to Simulate the Effect of Optical Proximity on MOSFET Parametric Yied," Proc. IEDM, 1999, pp. 913-916. Also: Patent pending.
9. th Meeting of The Electrochem. Soc., May 2001, accepted. Also: Patent pending.
10. A. Balasinski and D. Coburn, "Comparison of Mask Writing Tools and Mask Simulations for 0.16 um Devices," Proc. ASMC 1999, pp. 372-377.
11. Sequoia Device Designer User's Guide, Sequoia Design Systems, 1999.
12. See SRAM cell related papers in Proc. VLSI 1998, 1999, 2000.
13. See SRAM cell related papers in Proc. IEDM 1998, 1999, 2000.
14. V. Axelrad, N. Cobb, M. O'Brien, V. Boksha, T. Do, T. Donelly, Y. Granik, E. Sahouria, and A. Balasinski, "Efficient Full Chip Analysis Methodology for OPC-Corrected VLSI Designs," Proc. IEEE ISQED 2000, pp. 461-466.
15. 2, 6T Bulk Cell Technology for High Speed SRAMs," Proc. VLSI, 1993, pp. 65-66.