Standard cell characterization considering lithography induced variations

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 801-804

  Cao, Ke ^a   Dobre, Sorin ^a   Hu, Jiang ^b  

^a QUALCOMM INC   (United States)

^b TEXAS A AND M UNIVERSITY   (United States)

Author keywords

CAD; Design flow; OPC; Process CD; RET; Standard cell

Indexed keywords

GATE DIELECTRICS; INTEGRATED CIRCUIT MANUFACTURE; LIGHT INTERFERENCE; LITHOGRAPHY; NANOELECTRONICS;

DESIGN FLOW; LOW POWER DESIGNS; OPTICAL PROXIMITY CORRECTION (OPC); STANDARD CELLS;

VLSI CIRCUITS;

EID: 33846564061     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147111     Document Type: Conference Paper

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