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Volumn , Issue , 2008, Pages 808-811

Re-examining the use of Network-on-Chip as test access mechanism

Author keywords

[No Author keywords available]

Indexed keywords

CHLORINE COMPOUNDS; COST EFFECTIVENESS; ELECTRIC NETWORK TOPOLOGY; EMBEDDED SYSTEMS; INDUSTRIAL ENGINEERING; MECHANISMS; RHENIUM;

EID: 49749120586     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484917     Document Type: Conference Paper
Times cited : (16)

References (16)
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    • A. M. Amory, et al. DfT for the Reuse of Networks-on-Chip as Test Access Mechanism. In Proc. VTS, pp. 435-440, 2007.
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  • 2
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    • Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
    • A. M. Amory, et al. Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism. In Proc. ETS, pp. 213-218, 2006.
    • (2006) Proc. ETS , pp. 213-218
    • Amory, A.M.1
  • 3
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    • A survey of research and practices of network-on-chip
    • T. Bjerregaard and S. Mahadevan. A survey of research and practices of network-on-chip. ACM Comput. Surv., 38(1):1-54, 2006.
    • (2006) ACM Comput. Surv , vol.38 , Issue.1 , pp. 1-54
    • Bjerregaard, T.1    Mahadevan, S.2
  • 4
    • 0012157888 scopus 로고    scopus 로고
    • Optimal Test Access Architectures for System-on-a-Chip
    • Jan
    • K. Chakrabarty. Optimal Test Access Architectures for System-on-a-Chip. ACM TODAES, 6(1):26-49, Jan. 2001.
    • (2001) ACM TODAES , vol.6 , Issue.1 , pp. 26-49
    • Chakrabarty, K.1
  • 5
    • 30744455761 scopus 로고    scopus 로고
    • Reusing an on-chip network for the test of core-based systems
    • E. Cota, L. Carro, and M. Lubaszewski. Reusing an on-chip network for the test of core-based systems. ACM TODAES, 9(4):471-499, 2004.
    • (2004) ACM TODAES , vol.9 , Issue.4 , pp. 471-499
    • Cota, E.1    Carro, L.2    Lubaszewski, M.3
  • 6
    • 0005467492 scopus 로고    scopus 로고
    • Route Packets, Not Wires: On-Chip Interconnection Networks
    • W. J. Dally and B. Towles. Route Packets, Not Wires: On-Chip Interconnection Networks. In Proc. DAC, pp. 18-22, 2001.
    • (2001) Proc. DAC , pp. 18-22
    • Dally, W.J.1    Towles, B.2
  • 7
    • 44149107193 scopus 로고    scopus 로고
    • Crosstalk- and SEU-Aware Networks on Chips
    • Apr
    • A. P. Frantz, et al. Crosstalk- and SEU-Aware Networks on Chips. IEEE D&T, 24(4):340-350, Apr. 2007.
    • (2007) IEEE D&T , vol.24 , Issue.4 , pp. 340-350
    • Frantz, A.P.1
  • 8
    • 0036444568 scopus 로고    scopus 로고
    • Effective and Efficient Test Architecture Design for SOCs
    • S. K. Goel and E. J. Marinissen. Effective and Efficient Test Architecture Design for SOCs. In Proc. ITC, pp. 529-538, 2002.
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    • Goel, S.K.1    Marinissen, E.J.2
  • 9
    • 34047176072 scopus 로고    scopus 로고
    • The Æthereal network on chip: Concepts, architectures, and implementations
    • Sept-Oct
    • K. Goossens, J. Dielissen, and A. Rǎdulescu. The Æthereal network on chip: Concepts, architectures, and implementations. IEEE D&T, 22(5):21-31, Sept-Oct 2005.
    • (2005) IEEE D&T , vol.22 , Issue.5 , pp. 21-31
    • Goossens, K.1    Dielissen, J.2    Rǎdulescu, A.3
  • 10
    • 34548809233 scopus 로고    scopus 로고
    • Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints
    • F. A. Hussin, T. Yoneda, and H. Fujiwara. Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. In Proc. ETS, pp. 35-42, 2007.
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    • Hussin, F.A.1    Yoneda, T.2    Fujiwara, H.3
  • 11
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    • Co-Optimization of Test Wrapper and Test Access Architecture for Embedded Cores
    • Apr
    • V. Iyengar, K. Chakrabarty, and E. J. Marinissen. Co-Optimization of Test Wrapper and Test Access Architecture for Embedded Cores. JETTA, 18(2):213-230, Apr. 2002.
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    • Iyengar, V.1    Chakrabarty, K.2    Marinissen, E.J.3
  • 12
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    • Test Scheduling for Network-on-Chip with BIST and Precedence Constraints
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  • 13
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    • E. J. Marinissen, V. Iyengar, and K. Chakrabarty. A Set of Benchmarks for Modular Testing of SOCs. In Proc. ITC, pp. 519-528, 2002.
    • E. J. Marinissen, V. Iyengar, and K. Chakrabarty. A Set of Benchmarks for Modular Testing of SOCs. In Proc. ITC, pp. 519-528, 2002.
  • 15
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    • Jan
    • Q. Xu and N. Nicolici. Resource-Constrained System-on-a-Chip Test: A Survey. IEE PCDT, 152(1):67-81, Jan. 2005.
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    • Xu, Q.1    Nicolici, N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.