Minimizing virtual channel buffer for routers in on-chip communication architectures

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 1238-1243

  Al Faruque, Mohammad Abdullah ^a   Henkel, Jörg ^a  

^a UNIVERSITY OF KARLSRUHE   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; CELLULAR AUTOMATA; COMMUNICATION CHANNELS (INFORMATION THEORY); CONFORMAL MAPPING; ELECTRIC NETWORK TOPOLOGY; INDUSTRIAL ENGINEERING; MACHINE DESIGN; MICROPROCESSOR CHIPS; MULTI AGENT SYSTEMS; OPTIMIZATION; SPACE RESEARCH; TESTING;

ANT COLONY OPTIMIZATION ALGORITHMS; DESIGN SPACE EXPLORATION; DESIGN TIME; EMBEDDED APPLICATIONS; LOGICAL CHANNELS; NOVEL METHODOLOGY; ON-CHIP COMMUNICATION ARCHITECTURES; PROBABILISTIC APPROACHES; QOS PARAMETERS; SUPPORTED ON-CHIP COMMUNICATION; SWARM INTELLIGENCE; SYSTEM-ON-CHIP; TRAFFIC MODELLING; VIRTUAL CHANNELS;

ROUTERS;

EID: 49749106586     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484848     Document Type: Conference Paper

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