A two-step genetic algorithm for mapping task graphs to a network on chip architecture

Proceedings - Euromicro Symposium on Digital System Design, DSD 2003

Volumn , Issue , 2003, Pages 180-187

  Lei, Tang ^a   Kumar, S ^a  

^a JÖNKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; GENETIC ALGORITHMS; GRAPH ALGORITHMS; MAPPING; NETWORK ARCHITECTURE; REUSABILITY; SERVERS; SYSTEMS ANALYSIS;

COMMUNICATION DELAYS; COMPUTATIONAL RESOURCES; CORE BASED SYSTEM ON CHIPS; NETWORK-ON-CHIP ARCHITECTURES; NETWORK-ON-CHIP(NOC); NOC ARCHITECTURES; OVERALL EXECUTION; PARAMETERIZED TASK GRAPHS;

NETWORK-ON-CHIP;

ALGORITHMS; COMPUTATION; ELECTRIC CIRCUITS;

EID: 84944322013     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2003.1231923     Document Type: Conference Paper

References (10)

1. Luca Benini, and Giovanni De Micheli, "Network on Chips: A New SoC Paradigm", IEEE Computer, January 2002, pp. 70-78.
2. Axel Jantsch, and Hannu Tenhunen (Editors), Networks on Chip, Kluwer Academic Publishers, Boston, USA, January 2003.
3. thDesign Automation Conference, ACM/IEEE, Las Vegas, Nevada, USA, June 2001, pp. 673-677.
4. thDesign Automation Conference, ACM/IEEE, Las Vegas, Nevada, USA, June 2001, pp. 684-689.
5. nd Workshop on Embedded Systems, October, 2001.
6. Shashi Kumar et. al., "A Network on Chip Architecture and Design Methodology", IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, Pennsylvania, USA, April 2002, pp. 117-124.
7. thInternational Conference on VLSI Design 2003, IEEE, New Delhi, India, January 2003, pp. 401-408.
8. John H. Holland, Adaptation in Natural and Artificial Systems, MIT Press, Cambridge, MA, second edition, 1992.
9. thInternational Conference on VLSI Design, IEEE, Hyderabad, Inidia, 1997, pp. 155-160.
10. thInternational Workshop on Hardware/software Co-design, Seattle, Washington, USA, March 1998, pp.97-101.