MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2008, Pages 77-82

  Paul, Somnath ^a   Bhunia, Swamp ^a  

^a CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

FPGA; Memory based computing; Nanoscale crossbar; Reconfigurable architecture

Indexed keywords

BOTTOM-UP DESIGN; COMPUTING ELEMENTS; COMPUTING POWERS; DEFECT TOLERANCE; DESIGN AUTOMATION CONFERENCE; DESIGN COSTS; FPGA; FPGA IMPLEMENTATIONS; INTEGRATION DENSITIES; LOGIC BLOCKS; LOOK-UP-TABLES; MEMORY ARRAY DESIGN; MEMORY ARRAYS; MEMORY BASED COMPUTING; MULTI-INPUT MULTI-OUTPUT; NANO SCALING; NANO-COMPUTING; NANO-DEVICES; NANO-SCALE DEVICES; NANOSCALE CROSSBAR; PROGRAMMABLE INTERCONNECTS; RE-CONFIGURABLE; RE-CONFIGURABLE COMPUTING; RECONFIGURABLE ARCHITECTURE; REGULAR STRUCTURES; SCALABLE MEMORY; SIMULATION RESULTS; SOUTH PACIFIC; SYSTEM DESIGNS; TIME-MULTIPLEXED;

COMPUTER AIDED DESIGN; DEFECT DENSITY; DIGITAL INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INDUSTRIAL ENGINEERING; LOGIC CIRCUITS; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; OPTICAL DESIGN; SWITCHING CIRCUITS; SWITCHING THEORY;

DATA STORAGE EQUIPMENT;

EID: 49549100850     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2008.4484057     Document Type: Conference Paper

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