Surface potential and morphology issues of annealed (HfO 2) x(SiO 2) 1-x gate oxides

Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures

Volumn 22, Issue 4, 2004, Pages 2113-2120

  Ludeke, R ^a   Lysaght, P ^b   Cartier, E ^a   Gusev, E ^a   Chudzik, M ^c   Foran, B ^b   Bersuker, G ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b SEMATECH   (United States)

^c IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC LAYER DEPOSITION (ALD); CHANNEL CURRENT; CONTACT POTENTIAL DIFFERENCE (CPD); SURFACE POTENTIAL;

ANNEALING; ATOMIC FORCE MICROSCOPY; CRYSTALLIZATION; DATA ACQUISITION; DIELECTRIC MATERIALS; ELECTRIC FIELDS; LEAKAGE CURRENTS; MICROSTRUCTURE; SILICA; SURFACE PROPERTIES; THERMODYNAMIC STABILITY; TRANSMISSION ELECTRON MICROSCOPY; VACUUM;

HAFNIUM COMPOUNDS;

EID: 4944225104     PISSN: 10711023     EISSN: None     Source Type: Journal    
DOI: 10.1116/1.1771673     Document Type: Conference Paper

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22. -2 buried 2 nm below the surface (the center of the dielectric layer), assuming an effective k=10. This approximation is valid as long as d+z are small compared to the lateral extent of σ.