메뉴 건너뛰기




Volumn 29, Issue 8, 2008, Pages 889-891

Novel gate-all-around poly-Si TFTs with multiple nanowire channels

Author keywords

Gate all around (GAA); Nanowire; Poly Si; Thin film transistors (TFTs); Three dimensional (3 D) device

Indexed keywords

ELECTRIC WIRE; MOSFET DEVICES; NANOSTRUCTURED MATERIALS; NANOWIRES; OPTICAL DESIGN; POLYSILICON; SILICON; THIN FILM TRANSISTORS;

EID: 48649100588     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.2001176     Document Type: Article
Times cited : (57)

References (22)
  • 1
    • 33747566850 scopus 로고    scopus 로고
    • 3-D ICs: A novel chip design for improving deep sub-micrometer interconnect performance and system-on-chip integration
    • May
    • K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, "3-D ICs: A novel chip design for improving deep sub-micrometer interconnect performance and system-on-chip integration," Proc. IEEE, vol. 89, no. 5, pp. 602-633, May 2001.
    • (2001) Proc. IEEE , vol.89 , Issue.5 , pp. 602-633
    • Banerjee, K.1    Souri, S.J.2    Kapur, P.3    Saraswat, K.C.4
  • 2
    • 33847696913 scopus 로고    scopus 로고
    • 0.1 #m poly-Si thin film transistors for system-on-panel (SoP) applications
    • B.-Y. Tsui, C.-P. Lin, C.-F. Huang, and Y.-H. Xiao, "0.1 #m poly-Si thin film transistors for system-on-panel (SoP) applications," in IEDM Tech. Dig., 2005, pp. 911-914.
    • (2005) IEDM Tech. Dig , pp. 911-914
    • Tsui, B.-Y.1    Lin, C.-P.2    Huang, C.-F.3    Xiao, Y.-H.4
  • 3
    • 0026151511 scopus 로고
    • Avalanche-induced effects in polysilicon thinfilm transistors
    • May
    • M. Hack and A. G. Lewis, "Avalanche-induced effects in polysilicon thinfilm transistors," IEEE Electron Device Lett., vol. 12, no. 5, pp. 203-205, May 1991.
    • (1991) IEEE Electron Device Lett , vol.12 , Issue.5 , pp. 203-205
    • Hack, M.1    Lewis, A.G.2
  • 4
    • 0343526917 scopus 로고    scopus 로고
    • Unified model for short-channel poly-Si TFTs
    • Oct
    • B. Iñiguez, Z. Xu, T. A. Fjeldly, and M. S. Shur, "Unified model for short-channel poly-Si TFTs," Solid State Electron., vol. 43, no. 10, pp. 1821-1831, Oct. 1999.
    • (1999) Solid State Electron , vol.43 , Issue.10 , pp. 1821-1831
    • Iñiguez, B.1    Xu, Z.2    Fjeldly, T.A.3    Shur, M.S.4
  • 7
    • 0036999661 scopus 로고    scopus 로고
    • Multiple-gate SOI MOSFETs: Device design guidelines
    • Dec
    • J.-T. Park and J.-P. Colinge, "Multiple-gate SOI MOSFETs: Device design guidelines," IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2222-2229, Dec. 2002.
    • (2002) IEEE Trans. Electron Devices , vol.49 , Issue.12 , pp. 2222-2229
    • Park, J.-T.1    Colinge, J.-P.2
  • 10
    • 23744500528 scopus 로고    scopus 로고
    • 3 plasma passivation on electrical characteristics of polysilicon thin-film transistors by pattern-dependent metal-induced lateral crystallization
    • 3 plasma passivation on electrical characteristics of polysilicon thin-film transistors by pattern-dependent metal-induced lateral crystallization," J. Electrochem. Soc., vol. 152, no. 7, pp. G545-G549, 2005.
    • (2005) J. Electrochem. Soc , vol.152 , Issue.7
    • Wu, Y.-C.1    Chang, T.-C.2    Chou, C.-W.3    Wu, Y.-C.4    Liu, P.-T.5    Tu, C.-H.6    Lou, J.-C.7    Chang, C.-Y.8
  • 12
    • 34247853204 scopus 로고    scopus 로고
    • Operations of poly-Si nanowire thin-film transistors with a multiple-gated configuration
    • May
    • C.-J. Su, H.-C. Lin, H.-H. Tsai, H.-H. Hsu, T.-M. Wang, T.-Y. Huang, and W.-X. Ni, "Operations of poly-Si nanowire thin-film transistors with a multiple-gated configuration," Nanotechnology, vol. 18, no. 21, pp. 1-7, May 2007.
    • (2007) Nanotechnology , vol.18 , Issue.21 , pp. 1-7
    • Su, C.-J.1    Lin, H.-C.2    Tsai, H.-H.3    Hsu, H.-H.4    Wang, T.-M.5    Huang, T.-Y.6    Ni, W.-X.7
  • 13
    • 0036163060 scopus 로고    scopus 로고
    • Nanoscale CMOS spacer FinFET for the terabit era
    • Jan
    • Y.-K. Choi, T.-J. King, and C. Hu, "Nanoscale CMOS spacer FinFET for the terabit era," IEEE Electron Device Lett., vol. 23, no. 1, pp. 25-27, Jan. 2002.
    • (2002) IEEE Electron Device Lett , vol.23 , Issue.1 , pp. 25-27
    • Choi, Y.-K.1    King, T.-J.2    Hu, C.3
  • 14
    • 0030735702 scopus 로고    scopus 로고
    • 3 plasma passivation on n-channel polycrystalline silicon thin-film transistors
    • Jan
    • 3 plasma passivation on n-channel polycrystalline silicon thin-film transistors," IEEE Trans. Electron Devices, vol. 44, no. 1, pp. 64-68, Jan. 1997.
    • (1997) IEEE Trans. Electron Devices , vol.44 , Issue.1 , pp. 64-68
    • Cheng, H.-C.1    Wang, F.-S.2    Huang, C.-Y.3
  • 16
    • 0033892819 scopus 로고    scopus 로고
    • Ultra-thin elevated channel poly-Si TFT technology for fully-integrated AMLCD system on glass
    • Mar
    • S. Zhang, C. Zhu, J. K. O. Sin, J. N. Li, and P. K. T. Mok, "Ultra-thin elevated channel poly-Si TFT technology for fully-integrated AMLCD system on glass," IEEE Trans. Electron Devices, vol. 47, no. 3, pp. 569-575, Mar. 2000.
    • (2000) IEEE Trans. Electron Devices , vol.47 , Issue.3 , pp. 569-575
    • Zhang, S.1    Zhu, C.2    Sin, J.K.O.3    Li, J.N.4    Mok, P.K.T.5
  • 17
    • 33747989104 scopus 로고    scopus 로고
    • Analysis of width edge effects in advanced isolation schemes for deep submicron CMOS technologies
    • Nov
    • P. Sallagoity, M. Ada-Hanifi, M. Paoli, and M. Haond, "Analysis of width edge effects in advanced isolation schemes for deep submicron CMOS technologies," IEEE Trans. Electron Devices, vol. 43, no. 11, pp. 1900-1906, Nov. 1996.
    • (1996) IEEE Trans. Electron Devices , vol.43 , Issue.11 , pp. 1900-1906
    • Sallagoity, P.1    Ada-Hanifi, M.2    Paoli, M.3    Haond, M.4
  • 18
    • 84907707336 scopus 로고    scopus 로고
    • Comer effect in double and triple gate Fin-FETs
    • A. Burenkov and J. Lorenz, "Comer effect in double and triple gate Fin-FETs," in Proc. 33rd ESSDERC, 2003, pp. 135-138.
    • (2003) Proc. 33rd ESSDERC , pp. 135-138
    • Burenkov, A.1    Lorenz, J.2
  • 19
    • 0020089602 scopus 로고
    • Conductivity behavior in polycrystalline semiconductor thin film transistors
    • Feb
    • J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, "Conductivity behavior in polycrystalline semiconductor thin film transistors," J. Appl. Phys., vol. 53, no. 2, pp. 1193-1202, Feb. 1982.
    • (1982) J. Appl. Phys , vol.53 , Issue.2 , pp. 1193-1202
    • Levinson, J.1    Shepherd, F.R.2    Scanlon, P.J.3    Westwood, W.D.4    Este, G.5    Rider, M.6
  • 21
    • 0008923349 scopus 로고    scopus 로고
    • Novel self-aligned LDD/offset structure for poly-Si thin film transistors
    • W. Y. So, K. J. Yoo, S. I. Park, H. D. Kim, B. H. Kim, and H. K. Chung, "Novel self-aligned LDD/offset structure for poly-Si thin film transistors," in Proc. SID, 2001, pp. 1250-1253.
    • (2001) Proc. SID , pp. 1250-1253
    • So, W.Y.1    Yoo, K.J.2    Park, S.I.3    Kim, H.D.4    Kim, B.H.5    Chung, H.K.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.