-
1
-
-
33747566850
-
3-D ICs: A novel chip design for improving deep sub-micrometer interconnect performance and system-on-chip integration
-
May
-
K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, "3-D ICs: A novel chip design for improving deep sub-micrometer interconnect performance and system-on-chip integration," Proc. IEEE, vol. 89, no. 5, pp. 602-633, May 2001.
-
(2001)
Proc. IEEE
, vol.89
, Issue.5
, pp. 602-633
-
-
Banerjee, K.1
Souri, S.J.2
Kapur, P.3
Saraswat, K.C.4
-
2
-
-
33847696913
-
0.1 #m poly-Si thin film transistors for system-on-panel (SoP) applications
-
B.-Y. Tsui, C.-P. Lin, C.-F. Huang, and Y.-H. Xiao, "0.1 #m poly-Si thin film transistors for system-on-panel (SoP) applications," in IEDM Tech. Dig., 2005, pp. 911-914.
-
(2005)
IEDM Tech. Dig
, pp. 911-914
-
-
Tsui, B.-Y.1
Lin, C.-P.2
Huang, C.-F.3
Xiao, Y.-H.4
-
3
-
-
0026151511
-
Avalanche-induced effects in polysilicon thinfilm transistors
-
May
-
M. Hack and A. G. Lewis, "Avalanche-induced effects in polysilicon thinfilm transistors," IEEE Electron Device Lett., vol. 12, no. 5, pp. 203-205, May 1991.
-
(1991)
IEEE Electron Device Lett
, vol.12
, Issue.5
, pp. 203-205
-
-
Hack, M.1
Lewis, A.G.2
-
4
-
-
0343526917
-
Unified model for short-channel poly-Si TFTs
-
Oct
-
B. Iñiguez, Z. Xu, T. A. Fjeldly, and M. S. Shur, "Unified model for short-channel poly-Si TFTs," Solid State Electron., vol. 43, no. 10, pp. 1821-1831, Oct. 1999.
-
(1999)
Solid State Electron
, vol.43
, Issue.10
, pp. 1821-1831
-
-
Iñiguez, B.1
Xu, Z.2
Fjeldly, T.A.3
Shur, M.S.4
-
5
-
-
0141761518
-
Tri-gate fully-depleted CMOS transistors: Fabrication, design and layout
-
B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, and R. Chau, "Tri-gate fully-depleted CMOS transistors: Fabrication, design and layout," in VLSI Symp. Tech. Dig., 2003, pp. 133-134.
-
(2003)
VLSI Symp. Tech. Dig
, pp. 133-134
-
-
Doyle, B.1
Boyanov, B.2
Datta, S.3
Doczy, M.4
Hareland, S.5
Jin, B.6
Kavalieros, J.7
Linton, T.8
Rios, R.9
Chau, R.10
-
6
-
-
4544367603
-
5 nm-gate nanowire FinFET
-
F.-L. Yang, D. H. Lee, H. Y. Chen, C. Y. Chang, S. D. Liu, C. C. Huang, T. X. Chung, H. W. Chen, C. C. Huang, Y. H. Liu, C. C. Wu, C. C. Chen, S. C. Chen, Y. T. Chen, Y. H. Chen, C. J. Chen, B. W. Chan, P. F. Hsu, J. H. Shieh, H. J. Tao, Y. C. Yeo, Y. Li, J. W. Lee, P. Chne, M. S. Liang, and C. Hu, "5 nm-gate nanowire FinFET," in VLSI Symp. Tech. Dig., 2004, pp. 196-197.
-
(2004)
VLSI Symp. Tech. Dig
, pp. 196-197
-
-
Yang, F.-L.1
Lee, D.H.2
Chen, H.Y.3
Chang, C.Y.4
Liu, S.D.5
Huang, C.C.6
Chung, T.X.7
Chen, H.W.8
Huang, C.C.9
Liu, Y.H.10
Wu, C.C.11
Chen, C.C.12
Chen, S.C.13
Chen, Y.T.14
Chen, Y.H.15
Chen, C.J.16
Chan, B.W.17
Hsu, P.F.18
Shieh, J.H.19
Tao, H.J.20
Yeo, Y.C.21
Li, Y.22
Lee, J.W.23
Chne, P.24
Liang, M.S.25
Hu, C.26
more..
-
7
-
-
0036999661
-
Multiple-gate SOI MOSFETs: Device design guidelines
-
Dec
-
J.-T. Park and J.-P. Colinge, "Multiple-gate SOI MOSFETs: Device design guidelines," IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2222-2229, Dec. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.12
, pp. 2222-2229
-
-
Park, J.-T.1
Colinge, J.-P.2
-
8
-
-
0036045162
-
50 nm-gate all around (GAA)-silicon on nothing (SON)-devices: A simple way to co-integration of GAA transistors with bulk MOSFET process
-
S. Monfray, T. Skotniki, Y. Morand, S. Descombes, P. Coronel, P. Mazoyer, S. Harrison, P. Ribot, A. Talbot, D. Dutartre, M. Haond, R. Palla, Y. Le Friec, F. Leverd, M. E. Nier, C. Vizioz, and D. Louis, "50 nm-gate all around (GAA)-silicon on nothing (SON)-devices: A simple way to co-integration of GAA transistors with bulk MOSFET process," in VLSI Symp. Tech. Dig., 2002, pp. 108-109.
-
(2002)
VLSI Symp. Tech. Dig
, pp. 108-109
-
-
Monfray, S.1
Skotniki, T.2
Morand, Y.3
Descombes, S.4
Coronel, P.5
Mazoyer, P.6
Harrison, S.7
Ribot, P.8
Talbot, A.9
Dutartre, D.10
Haond, M.11
Palla, R.12
Le Friec, Y.13
Leverd, F.14
Nier, M.E.15
Vizioz, C.16
Louis, D.17
-
9
-
-
36849066110
-
Sub-5 nm all-around gate FinFET for ultimate scaling
-
H. Lee, L.-E. Yu, S.-W. Ryu, J.-W. Han, K. Jeon, D.-Y. Jang, K.-H. Kim, J. Lee, J.-H. Kim, S. C. Jeon, G. S. Lee, J. S. Oh, Y. C. Park, W. H. Bae, H. M. Lee, J. M. Yang, J. J. Yoo, and Y.-K. Choi, "Sub-5 nm all-around gate FinFET for ultimate scaling," in VLSI Symp. Tech. Dig., 2006, pp. 58-59.
-
(2006)
VLSI Symp. Tech. Dig
, pp. 58-59
-
-
Lee, H.1
Yu, L.-E.2
Ryu, S.-W.3
Han, J.-W.4
Jeon, K.5
Jang, D.-Y.6
Kim, K.-H.7
Lee, J.8
Kim, J.-H.9
Jeon, S.C.10
Lee, G.S.11
Oh, J.S.12
Park, Y.C.13
Bae, W.H.14
Lee, H.M.15
Yang, J.M.16
Yoo, J.J.17
Choi, Y.-K.18
-
10
-
-
23744500528
-
3 plasma passivation on electrical characteristics of polysilicon thin-film transistors by pattern-dependent metal-induced lateral crystallization
-
3 plasma passivation on electrical characteristics of polysilicon thin-film transistors by pattern-dependent metal-induced lateral crystallization," J. Electrochem. Soc., vol. 152, no. 7, pp. G545-G549, 2005.
-
(2005)
J. Electrochem. Soc
, vol.152
, Issue.7
-
-
Wu, Y.-C.1
Chang, T.-C.2
Chou, C.-W.3
Wu, Y.-C.4
Liu, P.-T.5
Tu, C.-H.6
Lou, J.-C.7
Chang, C.-Y.8
-
11
-
-
48649100398
-
Poly-Si nanowire thin-film transistors with inverse-T gate
-
H.-H. Hsu, H.-C. Lin, J.-F. Huang, and C.-J. Su, "Poly-Si nanowire thin-film transistors with inverse-T gate," in Proc. Ext. Abstract SSDM, 2007, pp. 818-819.
-
(2007)
Proc. Ext. Abstract SSDM
, pp. 818-819
-
-
Hsu, H.-H.1
Lin, H.-C.2
Huang, J.-F.3
Su, C.-J.4
-
12
-
-
34247853204
-
Operations of poly-Si nanowire thin-film transistors with a multiple-gated configuration
-
May
-
C.-J. Su, H.-C. Lin, H.-H. Tsai, H.-H. Hsu, T.-M. Wang, T.-Y. Huang, and W.-X. Ni, "Operations of poly-Si nanowire thin-film transistors with a multiple-gated configuration," Nanotechnology, vol. 18, no. 21, pp. 1-7, May 2007.
-
(2007)
Nanotechnology
, vol.18
, Issue.21
, pp. 1-7
-
-
Su, C.-J.1
Lin, H.-C.2
Tsai, H.-H.3
Hsu, H.-H.4
Wang, T.-M.5
Huang, T.-Y.6
Ni, W.-X.7
-
13
-
-
0036163060
-
Nanoscale CMOS spacer FinFET for the terabit era
-
Jan
-
Y.-K. Choi, T.-J. King, and C. Hu, "Nanoscale CMOS spacer FinFET for the terabit era," IEEE Electron Device Lett., vol. 23, no. 1, pp. 25-27, Jan. 2002.
-
(2002)
IEEE Electron Device Lett
, vol.23
, Issue.1
, pp. 25-27
-
-
Choi, Y.-K.1
King, T.-J.2
Hu, C.3
-
14
-
-
0030735702
-
3 plasma passivation on n-channel polycrystalline silicon thin-film transistors
-
Jan
-
3 plasma passivation on n-channel polycrystalline silicon thin-film transistors," IEEE Trans. Electron Devices, vol. 44, no. 1, pp. 64-68, Jan. 1997.
-
(1997)
IEEE Trans. Electron Devices
, vol.44
, Issue.1
, pp. 64-68
-
-
Cheng, H.-C.1
Wang, F.-S.2
Huang, C.-Y.3
-
15
-
-
33646228385
-
Advanced poly-Si TFT with finlike channels by ELA
-
May
-
H. Yin, W. Xianyu, H. Cho, X. Zhang, J. Jung, D. Kim, H. Lim, K. Park, J. Kim, J. Kwon, and T. Noguchi, "Advanced poly-Si TFT with finlike channels by ELA," IEEE Electron Device Lett., vol. 27, no. 5, pp. 357-359, May 2006.
-
(2006)
IEEE Electron Device Lett
, vol.27
, Issue.5
, pp. 357-359
-
-
Yin, H.1
Xianyu, W.2
Cho, H.3
Zhang, X.4
Jung, J.5
Kim, D.6
Lim, H.7
Park, K.8
Kim, J.9
Kwon, J.10
Noguchi, T.11
-
16
-
-
0033892819
-
Ultra-thin elevated channel poly-Si TFT technology for fully-integrated AMLCD system on glass
-
Mar
-
S. Zhang, C. Zhu, J. K. O. Sin, J. N. Li, and P. K. T. Mok, "Ultra-thin elevated channel poly-Si TFT technology for fully-integrated AMLCD system on glass," IEEE Trans. Electron Devices, vol. 47, no. 3, pp. 569-575, Mar. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.3
, pp. 569-575
-
-
Zhang, S.1
Zhu, C.2
Sin, J.K.O.3
Li, J.N.4
Mok, P.K.T.5
-
17
-
-
33747989104
-
Analysis of width edge effects in advanced isolation schemes for deep submicron CMOS technologies
-
Nov
-
P. Sallagoity, M. Ada-Hanifi, M. Paoli, and M. Haond, "Analysis of width edge effects in advanced isolation schemes for deep submicron CMOS technologies," IEEE Trans. Electron Devices, vol. 43, no. 11, pp. 1900-1906, Nov. 1996.
-
(1996)
IEEE Trans. Electron Devices
, vol.43
, Issue.11
, pp. 1900-1906
-
-
Sallagoity, P.1
Ada-Hanifi, M.2
Paoli, M.3
Haond, M.4
-
18
-
-
84907707336
-
Comer effect in double and triple gate Fin-FETs
-
A. Burenkov and J. Lorenz, "Comer effect in double and triple gate Fin-FETs," in Proc. 33rd ESSDERC, 2003, pp. 135-138.
-
(2003)
Proc. 33rd ESSDERC
, pp. 135-138
-
-
Burenkov, A.1
Lorenz, J.2
-
19
-
-
0020089602
-
Conductivity behavior in polycrystalline semiconductor thin film transistors
-
Feb
-
J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, "Conductivity behavior in polycrystalline semiconductor thin film transistors," J. Appl. Phys., vol. 53, no. 2, pp. 1193-1202, Feb. 1982.
-
(1982)
J. Appl. Phys
, vol.53
, Issue.2
, pp. 1193-1202
-
-
Levinson, J.1
Shepherd, F.R.2
Scanlon, P.J.3
Westwood, W.D.4
Este, G.5
Rider, M.6
-
20
-
-
0022119783
-
Anomalous leakage current in LPCVD poly-silicon MOSFETs
-
Sep
-
J. G. Fossum, A. Ortiz-Conde, H. Shicjijo, and S. K. Banerjee, "Anomalous leakage current in LPCVD poly-silicon MOSFETs," IEEE Trans. Electron Devices, vol. 32, no. ED-9, pp. 1878-1884, Sep. 1985.
-
(1985)
IEEE Trans. Electron Devices
, vol.32
, Issue.ED-9
, pp. 1878-1884
-
-
Fossum, J.G.1
Ortiz-Conde, A.2
Shicjijo, H.3
Banerjee, S.K.4
-
21
-
-
0008923349
-
Novel self-aligned LDD/offset structure for poly-Si thin film transistors
-
W. Y. So, K. J. Yoo, S. I. Park, H. D. Kim, B. H. Kim, and H. K. Chung, "Novel self-aligned LDD/offset structure for poly-Si thin film transistors," in Proc. SID, 2001, pp. 1250-1253.
-
(2001)
Proc. SID
, pp. 1250-1253
-
-
So, W.Y.1
Yoo, K.J.2
Park, S.I.3
Kim, H.D.4
Kim, B.H.5
Chung, H.K.6
-
22
-
-
33750459850
-
A novel poly-Si thin film transistor with the in-situ vacuum gaps under the T-shaped-gated electrode
-
T.-C. Liao, C.-Y. Wu, F.-T. Chien, C.-C. Tsai, H.-H. Chen, C.-Y. Kung, and H.-C. Cheng, "A novel poly-Si thin film transistor with the in-situ vacuum gaps under the T-shaped-gated electrode," Electrochem. Solid-State Lett., vol. 9, no. 12, pp. G347-G350, 2006.
-
(2006)
Electrochem. Solid-State Lett
, vol.9
, Issue.12
-
-
Liao, T.-C.1
Wu, C.-Y.2
Chien, F.-T.3
Tsai, C.-C.4
Chen, H.-H.5
Kung, C.-Y.6
Cheng, H.-C.7
|