Control and datapath decoupling in the design of a NoC switch: Area, power and performance implications

2007 International Symposium on System-on-Chip Proceedings, SOC

Volumn , Issue , 2007, Pages

  Medardoni, Simone ^a   Bertozzi, Davide ^a   Benini, Luca ^b   Macii, Enrico ^c  

^a UNIVERSITY OF FERRARA   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

^c POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ASYNCHRONOUS SEQUENTIAL LOGIC; COMMUNICATION; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; TECHNOLOGY;

DATA PATHS; DESIGN POINTS; DISRUPTIVE TECHNOLOGIES; IN-CONTROL; INTENSIVE RESEARCH; INTERNATIONAL SYMPOSIUM; LOGIC SYNTHESIS TOOLS; LOW POWER TECHNOLOGIES; LOW POWERS; NANO SCALING; NETWORK BUILDING BLOCKS; NETWORKS ON CHIPS; NOC SWITCH; ON-CHIP COMMUNICATIONS; SPECIFIC DESIGN; SWITCH ARCHITECTURES; SYSTEM ON CHIPS;

LOGIC DESIGN;

EID: 48049101920     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSOC.2007.4427438     Document Type: Conference Paper

References (22)

1. J.Kim et al., "A low latency router supporting adaptivity for on-chip interconnects", DAC, pp.559-564, 2005.
2. S.Stergiou et al., "Xpipes Lite: a Synthesis Oriented Design Library for Networks on Chips', DAC, pp.559-564, 2005.
3. J.Kim et al., "A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks", Int.Symp.on Computer Architecture, pp.4-15, 2006.
4. Rijpkema, E. et al., Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip, in Computers and Digital Techniques, IEE Proceedings, Volume 150, Issue 5,22 Sept. 2003 Page(s): 294-302.
5. S.Sathe, D.Wiklund, D.Liu, Design of a switching node (router) for on-chip networks. Int. Conf. on ASIC, pp.75-78, 2003.
6. D.Wiklund, D.Liu, SoCBUS: Switched network on chip for hard real time embedded systems, in Proc. of IPDPS, 2003, pp.78a.
7. P.T.Wolkotte et al. An energy-efficient reconfigurable circuit-switched network-on-chip, in Proc. of IPDPS, 2005, pp. 155a.
8. A.Ahmadinia et al., A practical approach for circuit routing on dynamic reconfigurable devices, in Proc. of RSP, 2005, pp.84-90.
9. P.H.Pham, Y.Kumar, C.Kim, High performance and area-efficient oircuit-awitched network on chip design, in Proc, of CIT06, 2006.
10. Q. Ye, J.Liu, L.R.Zheng, Switoh Design and Implementation for Network-on-Chip, Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, June 2005, pp.1-7.
11. A.Banerjee, R.Mullins, S.Moore, A power and energy exploration of network-on-chip architectures, in International Symposium on Networks-on-Chip, 2007. May 2007, pp.163-172.
12. F.Angiolini, P.Meloni, S.Carta, L.Benini, L.Raffo, Contrasting a NoC and a traditional interconnect fabric with layout awareness, in Design Automation and Test in Europe Conference, 2006, pp.124-129.
13. A.Pullini et al., NoC design and implementation in 65nm technology, Int. Symposium on Networks-on-Chip, 2007, pp.273-282.
14. F.Steenhof et al., Networks on Chips for high-end consumer-electronics TV system architectures, DATE, 2006, pp.148-153.
15. D.Bertozzi, Network interface architecture and design issues, book chapter from Networks on Chips: Technology and Tools, Morgan Kaufmann, 2006, San Francisco (USA).
16. H.Wang, X.Zhu, L.S.Peh, S.Malik, Orion: a power-performance simulator for interconnection networks, in ACM/IEEE MICRO, Nov. 2002, pp.294-305.
17. K.Lee, S.J.Lee, H.J.Yoo, Low-power network-on-chip for high-performance SoC design, IEEE Transactions on VLSI Systems, vol.14, no. 2, pp.148-160, 2006.
18. X,Chen, L.S.Peh, Leakage power modelling and optimization in interconnection networks, ISLPED 2003, pp.90-95.
19. S.Medardoni, D.Bertozzi, E.Macii, Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies, to be presented at ISLPED 2007.
20. J.Xi, P.Zhong, A transaction-level NoC simulation platform with architecture-level dynamic and leakage energy models, GLSVLSI 2006, pp. 341-344.
21. N.Banerjee, P.Vellanki, K.S.Chatha, A power and performance model for network-on-chip architectures, DATE 2004, pag.21250.
22. A.Pullini et al., "Fault tolerance overhead in network-on-chip flow oontrol schemes", SBCCI, pp.224-229, 2005.