Design of a switching node (router) for on-chip networks

IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings

Volumn 1, Issue , 2003, Pages 75-78

  Sathe, Sumant ^a   Wiklund, Daniel ^a   Liu, Dake ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

DATA TRANSFER;

BASIC BUILDING BLOCK; CMOS TECHNOLOGY; HARDWARE BLOCKS; KEY ELEMENTS; ON-CHIP NETWORKS; PROTOTYPE DESIGNS; SWITCHING NODES;

SWITCHING;

EID: 33745794830     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASIC.2003.1277494     Document Type: Conference Paper

References (8)

1. D. Wiklund and D. Liu. "SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems". in IPDPS 2003.
2. E. Rijpkema, et. al. "Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip", in DATE 2003.
3. Saastamoinen, et. al. "Interconnect IP Node for Future System-on-Chip Designs", in IEEE Internal Workshop on Electronic Design, Test and Applications, 2002.
4. P. Guerrier and A. Greiner. "A generic architecture for on-chip packet-switched interconnections", in DATE 2000.
5. W. J. Dally and B. Towles. "Route packets, not wires: On-chip interconnection networks", in DAC 2001.
6. L. Benini and G. De Micheli. "Networks on Chips: A New SoC Paradigm", in IEEE Computer, 35(1):70-78, 2002.
7. K. Goossens, et. al. "Networks on silicon". "Combining best-effort and guaranteed services", in DATE 2002.
8. F. Mu and C. Svensson. "Self-Tested Self-Synchronization Circuit for Mesochronous Clocking", in IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 48, no. 2, Feb. 2001.