Data-reuse-driven energy-aware cosynthesis of scratch pad memory and hierarchical bus-based communication architecture for multiprocessor streaming applications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 8, 2008, Pages 1439-1452

  Issenin, Ilya ^a,b,c   Brockmeyer, Erik ^d   Durinck, Bart ^d,e   Dutt, Nikil D ^a,b,f  

^a IEEE

^b Irvine   (United States)

^c Teradek   (United States)

^d IMEC   (Belgium)

^e ARM Belgium   (Belgium)

^f UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Bus synthesis; Data reuse; Embedded systems; Hierarchical bus based communication architecture; Memory optimizations; Multiprocessor scratch pad memory (SPM) hierarchy

Indexed keywords

ARCHITECTURE; ARSENIC; ARSENIC COMPOUNDS; BENCHMARKING; BREEDER REACTORS; BUSES; COMMUNICATION; CONSERVATION; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; FAULT TOLERANCE; HEURISTIC METHODS; HEURISTIC PROGRAMMING; INTEGER PROGRAMMING; INTEGRATED CIRCUITS; LINEAR PROGRAMMING; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; QUALITY ASSURANCE; REAL TIME SYSTEMS; RELIABILITY; WIRELESS SENSOR NETWORKS;

BUS-BASED COMMUNICATION; COMMUNICATION ARCHITECTURES; COMMUNICATION SYNTHESIS; COMPILE TIME; DATA REUSING; EMBEDDED APPLICATIONS; ENERGY AWARE; ENERGY EFFICIENT; GUARANTEED THROUGHPUT (GT); HEURISTIC APPROACHES; MEMORY ACCESSES; MEMORY ARCHITECTURE(MA); MIXED INTEGERS; MULTI PROCESSOR SYSTEMS; MULTIPROCESSOR SYSTEMS-ON-CHIP (MPSOC); OPTIMAL RESULTS; POWER CONSUMPTION (CE); POWER EFFICIENCIES; SCRATCH-PAD MEMORY (SPM); STREAMING APPLICATIONS; SYNTHESIS TECHNIQUES; TECHNOLOGY ADVANCES; TWO STEP SYNTHESIS;

DATA STORAGE EQUIPMENT;

EID: 47849112050     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.925781     Document Type: Article

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