Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications

CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis

Volumn , Issue , 2006, Pages 294-299

  Issenin, Ilya ^a   Dutt, Nikil ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Communication synthesis; Customized memory hierarchy; Data reuse; Hierarchical TDMA buses; Multiprocessor system on chip

Indexed keywords

COMMUNICATION SYNTHESIS; MULTIPROCESSOR SYSTEMS-ON-CHIP (MPSOC); STREAMING APPLICATIONS;

DATA ACQUISITION; DATA STORAGE EQUIPMENT; ELECTRIC POWER UTILIZATION; HEURISTIC METHODS; MICROPROCESSOR CHIPS; TIME DIVISION MULTIPLE ACCESS;

MULTIPROCESSING SYSTEMS;

EID: 34547207162     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1176254.1176326     Document Type: Conference Paper

References (20)

1. Y. Aghaghiri et al. Irredundant address bus encoding for low power. In Proc. ISLPED 2001.
2. K. Banerjee, A. Mehrotra. A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs. IEEE Trans, on Electron Devices, vol. 49, no. 11, Nov 2002.
3. D. Burger and T. Austin. The SimpleScalar tool set, version 2.0. TR 1342, University of Wisconsin-Madison, CS Dept., 1997.
4. L. Cai et al. A Novel Memory Size Model for Variable-Mapping In System Level Design. ASP-DAC 2004.
5. Chen et al. Segmented Bus Design for Low-Power Systems. IEEE Trans, on VLSI Systems, vol.7, no.1, 1999.
6. CPLEXILP solver, www.cplex.com.
7. M. Gasteier, M. Glesner. Bus-based communication synthesis on system level. In ACM TODAES, Jan. 1999.
8. I. Issenin, E. Brockmeyer, B. Durinck, N. Dutt. Multiprocessor System-on-Chip Data Reuse Analysis for Exploring Customized Memory Hierarchies. In proc. of DAC, 2006.
9. S. Kim et al. Efficient Exploration of On-Chip Bus Architectures and Memory Allocation. CODES+ISSS, 2004
10. D. Lyonnard et al. Automatic generation of application- specificarchitectures for heterogeneous multiprocessor systemon-chip. In Proc. of DAC, 2001.
11. MPARM project, http://www-micrel.deis.unibo.it/sitonew/ research/mparm.html
12. S. Pasricha, N. Dutt. COSMECA: Application Specific CoSynthesis of Memory and Communication Architectures for MPSoC. In Proc. DATE 2006.
13. S. Pasricha et al. Automated Throughput-driven Synthesis of Bus-based Communication Architectures. ASPDAC 2005.
14. A. Pinto et al. Constraint-driven communication synthesis. In Proc. DAC 2002.
15. K. K. Ryu, V. J. Mooney III. Automated Bus Generation for Multiprocessor SoC Design. In Proc. of DATE 2003.
16. Sonics Inc. http://www.sonicsinc.com/sonics/products/siliconbackplaneIII/
17. P. Stobach. A new technique in scene adaptive coding. In Proc. of EUSIPCO, Grenoble, 1988.
18. H. Wang et al. Global Bus Power Optimization Methodology for Physical Design of Memory Dominated Systems by Coupling Bus Segmentation and Activity Driven Block Placement. In Proc. ASP-DAC 2004.
19. P. Wolkotte et al. Energy-Efficient NoC for Best-Effort Communication. ICFPLA, 2005.
20. H. Zhang, J. Rabaey. Low-swing interconnect interface circuits. In Proc. ISLPED, Aug. 1998.