메뉴 건너뛰기




Volumn 2005, Issue , 2005, Pages 197-202

Energy-efficient NOC for best-effort communication

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION SYSTEMS; COMPUTER ARCHITECTURE; LOGIC CIRCUITS; MULTIPROCESSING PROGRAMS; PACKET SWITCHING; THROUGHPUT;

EID: 33746868351     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2005.1515722     Document Type: Conference Paper
Times cited : (14)

References (13)
  • 1
    • 33746929334 scopus 로고    scopus 로고
    • http://www.smart-chips.com.
  • 2
    • 0000087207 scopus 로고
    • The semantics of a simple language for parallel programming
    • J. L. Rosenfeld, Ed. Stockholm, Sweden: North Holland, Amsterdam, Aug
    • G. Kahn, "The semantics of a simple language for parallel programming," in Information processing, J. L. Rosenfeld, Ed. Stockholm, Sweden: North Holland, Amsterdam, Aug 1974, pp. 471-475.
    • (1974) Information Processing , pp. 471-475
    • Kahn, G.1
  • 3
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new soc paradigm
    • January
    • L. Benini and G. de Micheli, "Networks on chips: A new soc paradigm," IEEE Computer, vol. 35, no. 1, pp. 70-78, January 2002.
    • (2002) IEEE Computer , vol.35 , Issue.1 , pp. 70-78
    • Benini, L.1    De Micheli, G.2
  • 4
    • 20844442766 scopus 로고    scopus 로고
    • Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture
    • December
    • L. T. Smit, et al., "Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture," in Proceedings of the International Conference on Field-Programmable Technology, December 2004.
    • (2004) Proceedings of the International Conference on Field-Programmable Technology
    • Smit, L.T.1
  • 11
    • 33746888532 scopus 로고    scopus 로고
    • http://www.synopsys.com.
  • 12
    • 33746898158 scopus 로고    scopus 로고
    • Comparative analysis of serial vs. parallel links in networks on chip
    • Tampere, Finland: IEEE Computer Society Press, Los Alamitos, California, November, iSBN 0-7803-8558-6
    • A. Morgenshtein, et al., "Comparative analysis of serial vs. parallel links in networks on chip," in Proceedings SOC 2004 International Symposium on System-on-Chip. Tampere, Finland: IEEE Computer Society Press, Los Alamitos, California, November 2004, iSBN 0-7803-8558-6.
    • (2004) Proceedings SOC 2004 International Symposium on System-on-Chip
    • Morgenshtein, A.1
  • 13
    • 0036866915 scopus 로고    scopus 로고
    • A power-optimal repeater insertion methodology for global interconnects in nanometer designs
    • November
    • K. Banerjee and A. Mehrotra, "A power-optimal repeater insertion methodology for global interconnects in nanometer designs," IEEE Transactions on Electron Devices, vol. 49, no. 11, pp. 2001-2007, November 2002.
    • (2002) IEEE Transactions on Electron Devices , vol.49 , Issue.11 , pp. 2001-2007
    • Banerjee, K.1    Mehrotra, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.