A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2004, Pages 759-761

  Wang, Hua ^b   Papanikolaou, Antonis ^a   Miranda, Miguel ^a   Catthoor, Francky ^b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CAPACITANCE; COMPUTATIONAL COMPLEXITY; DATA STORAGE EQUIPMENT; DATA TRANSFER; ELECTRIC POTENTIAL; MICROPROCESSOR CHIPS; OPTIMIZATION; SWITCHES;

MEMORY BUSES; MEMORY DOMINATED SYSTEMS; POWER CONSUMPTION;

COMPUTER SYSTEMS;

EID: 2442622338     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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