Efficient exploration of on-chip bus architectures and memory allocation

Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis, CODES+ISSS 2004

Volumn , Issue , 2004, Pages 248-253

  Kim, Sungchan ^a   Im, Chaeseok ^a   Ha, Soonhoi ^a  

^a Seoul National University   (South Korea)

Author keywords

Communication architecture optimization; Design space exploration; Memory allocation; System on a Chip

Indexed keywords

COMPUTER SIMULATION; EQUALIZERS; ITERATIVE METHODS; OPTIMIZATION; STORAGE ALLOCATION (COMPUTER); SYSTEMS ANALYSIS; TOPOLOGY;

BUS TOPOLOGY; COMMUNICATION ARCHITECTURE OPTIMIZATION; DESIGN SPACE EXPLORATION; SYSTEM-ON-A-CHIP (SOC);

MICROPROCESSOR CHIPS;

EID: 16244409292     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1016720.1016779     Document Type: Conference Paper

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