The multi-spacer patterning technique: A non-lithographic technique for terascale integration

Semiconductor Science and Technology

Volumn 23, Issue 7, 2008, Pages

  Cerofolini, G F ^a   Amato, P ^a   Romano, E ^b  

^a STMICROELECTRONICS   (Italy)

^b UNIVERSITY OF MILANO BICOCCA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON MULTIPLIERS; ELECTRONIC PROPERTIES; ELECTRONICS INDUSTRY; FIELD EFFECT SEMICONDUCTOR DEVICES; GATES (TRANSISTOR); INTEGRATED CIRCUITS; LITHOGRAPHY; METALS; MICROELECTRONICS; MOLECULAR ELECTRONICS; MOLECULES; MOSFET DEVICES; NANOTECHNOLOGY; NONMETALS; SEMICONDUCTING INDIUM; SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICES; SILICON; TRANSISTORS;

ELECTRONIC DEVICES; FIELD EFFECTS; METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET); MOLECULAR DESIGNS; MOLECULAR DEVICES; NANOMETRE; PATTERNING TECHNIQUES; PLANAR ARRANGEMENT; SILICON BASED DEVICES; TERASCALE INTEGRATION;

FIELD EFFECT TRANSISTORS;

EID: 47749098936     PISSN: 02681242     EISSN: 13616641     Source Type: Journal    
DOI: 10.1088/0268-1242/23/7/075020     Document Type: Article

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