An FPGA implementation of pipelined multiplicative division with IEEE Rounding

Proceedings 2007 IEEE Symposium on Field-Programme Custom Computing Machines, FCCM 2007

Volumn , Issue , 2007, Pages 185-194

  Goldberg, Ronen ^a   Eveny, Guy ^a   Seidelz, Peter M ^b  

^a TEL AVIV UNIVERSITY   (Israel)

^b Southern Methodist University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; COMPUTERS; DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FREQUENCY MULTIPLYING CIRCUITS;

CLOCK FREQUENCY; DIVISION CIRCUIT; DOUBLE PRECISION; FPGA IMPLEMENTATIONS; INITIAL APPROXIMATION; PIPELINE STAGES; RADIX-8 MULTIPLIER; RANDOM VECTORS;

PIPELINES;

EID: 47349092816     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2007.59     Document Type: Conference Paper

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