Improved small multiplier based multiplication, squaring and division

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2003-January, Issue , 2003, Pages 91-97

  Lee, B R ^a   Burgess, N ^a  

^a CARDIFF UNIVERSITY   (United Kingdom)

Author keywords

Buildings; Circuits; Concatenated codes; Delay; Design engineering; Embedded computing; Field programmable gate arrays; Logic; Table lookup

Indexed keywords

BUILDINGS; COMPUTERS; CONCATENATED CODES; DELAY CIRCUITS; LOGIC GATES; NETWORKS (CIRCUITS); TABLE LOOKUP;

DELAY; DESIGN ENGINEERING; EMBEDDED COMPUTING; FIXED-POINT INTEGER; FRACTIONAL DIVISION; LOGIC; MULTIPLIER BLOCKS; PARTIAL PRODUCT;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84872909725     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2003.1227245     Document Type: Conference Paper

References (8)

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8. M. D. Ercegovac and T. Lang, Division and Square-Root Algorithms. Kluwer Academic. 1994.