Parameterisable floating-point operations on FPGA

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 2002, Pages 1064-1068

  Lee, Barry ^a   Burgess, Neil ^a  

^a CARDIFF UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (STANDARDS); COMPUTATIONAL COMPLEXITY; DIGITAL ARITHMETIC; OPTIMIZATION;

LOGARITHMIC NUMBER SYSTEMS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0038305296     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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2. th Conference on Field Programmable Logic and Applications, pp. 657-666, 2002.
3. A. Jaenick and W. Luk, "Parameterised Floating-Point arithmetic on FPGAs", Proc. Acoustics, Speech and Signal Processing, IEEE, pp. 897-900, 2001.
4. IEEE standard for binary floating-point arithmetic ANSI/IEEE 754 1985.
5. th Symp. on Comp. Arith., pp. 184-194.
6. A. R. Omondi, "Computer Arithmetic Systems", Prentice Hall 1994.
7. B. Parhami, "Computer Arithmetic", Oxford University Press, 2000.
8. th Conference on Field Programmable Logic and Applications, pp. 513-522, 2002.
9. M. D. Ercegovac and T. Lang, "Division and Square-Root Algorithms". Kluwer Academic, 1994.