A formal model and efficient traversal algorithm for generating testbenches for verification of IEEE standard floating point division

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Matula, David W ^a   McFearin, Lee D ^a  

^a Southern Methodist University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL ARITHMETIC; RANDOM PROCESSES; STANDARDIZATION;

DESIGN SIMULATION; DIVISION ALGORITHM DESIGN; QUOTIENT ROUNDING BOUNDARIES; TESTBENCHES;

ALGORITHMS;

EID: 34047131764     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.243998     Document Type: Conference Paper

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