Scalable pipeline insertion in floating-point division and square root units

Midwest Symposium on Circuits and Systems

Volumn 2, Issue , 2004, Pages

  Ortiz, Irvin ^a   Jimenez, Manuel ^a  

^a UNIVERSITY OF PUERTO RICO   (Puerto Rico)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; FUNCTIONS; ITERATIVE METHODS; MATHEMATICAL OPERATORS; PARAMETER ESTIMATION;

FLOATING-POINT (FP) DIVISION; PIPELINE INSERTION; REGULAR STRUCTURES; SQUARE ROOT UNITS;

DATA PROCESSING;

EID: 11144302617     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. L. Dadda and V. Piuri. Pipelined adders. IEEE Transactions on Computers, pages 348 - 356, March 1996.
2. I. Klotchkov and S. Pedersen. A codesign case study: Implementing arithmetic functions in FPGAs. Symposium and Workshop on Engineering of Computer-Based Systems, pages 389 - 394, 1996.
3. I. Koren. Computer Arithmetic Algorithms. Brookside Court Publishers, Amherst, Massachusetts, 1998.
4. N. Limited. IEEE 754 Floating Point Core, www.nallatech.com, 2001.
5. S. Oberman and M. Flynn. Division algorithms and implementations. IEEE Transactions on Computers, vol. 46, no. 8., pages 833-854, AUGUST 1997.
6. I. Ortiz and M. Jimenez. Scalable pipeline insertion in floating point units for FPGA synthesis. Proceedings of the IASTED International Conference on Circuit, Signals, and Systems, pages 421-426, May 19-212003.
7. B. Parhami. Computer Arithmetic: Algorithms and Hardware Designs, chapter 18, pages 300-303. Oxford, 2000.
8. QinetiQ, www.quixilica.com. Quixilica Floating Point Cores, 2002.