Pipelined multiplicative division with IEEE rounding

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 240-245

  Even, Guy ^a   Seidel, Peter M ^b  

^a TEL AVIV UNIVERSITY   (Israel)

^b Southern Methodist University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; COMPUTATIONAL COMPLEXITY; DIGITAL ARITHMETIC; ERROR ANALYSIS; OPTIMIZATION; THEOREM PROVING;

BOOTH RADIX-8 MULTIPLICATION; DEWPOINT ROUNDING; GOLDSCHMIDT DIVISION ALGORITHM; PIPELINED MULTIPLICATIVE DIVISION; QUOTIENT APPROXIMATION;

MICROPROCESSOR CHIPS;

EID: 0344119459     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. M. Daumas and D. Matula. Recoders for partial compression and rounding. Technical Report 97-01, Laboratoire de l'Informatique du Prallélisme, Lyon, France, 1997.
2. G. Even, S. Mueller, and P. Seidel. A Dual Mode IEEE multiplier. In Proceedings of the 2nd IEEE International Conference on Innovative Systems in Silicon, pp 282-289 IEEE, 1997.
3. G. Even and P.-M. Seidel. Pipelined multiplicative division with IEEE rounding. Internal manuscript (full version), US patent pending, 2002.
4. G. Even, P.-M. Seidel, and W.E. Ferguson. A parametric error analysis of Goldschmidt's division algorithm, 2002.
5. R. Goldschmidt. Applications of division by convergence. Master's thesis, MIT, June 1964.
6. IEEE standard for binary floating-point arithmetic. ANSI/IEEE754-1985, New York, 1985.
7. S. F. Oberman. Floating-point division and square root algorithms and implementation in the AMD-K7 microprocessor. In Koren and Kornerup, editors, Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Adelaide, Australia), pp 106-115 Los Alamitos, CA, April 1999 IEEE Computer Society Press.
8. P.-M. Seidel. High-speed redundant reciprocal approximation. Integration, the VLSI Journal, 28: 1-12, 1999.