Design of a field-programmable dual-precision floating-point arithmetic unit

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2006, Pages 733-736

  Diniz, Pedro C ^a   Govindu, Gokul ^b  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b University of Southern California ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUZZY LOGIC; GENERAL PURPOSE COMPUTERS;

(+ MOD 2N) OPERATION; AND OPERATOR; ARITHMETIC CORES; CLOCK RATES; FIELD PROGRAMMABLE LOGIC (FPL); FLOATING POINT (FP); FLOATING POINT ARITHMETICS; FPGA DEVICES; GENERAL (CO); GENERAL PURPOSE PROCESSOR (GPP); HARDWARE RESOURCES; INTERNATIONAL CONFERENCES; PERFORMANCE POTENTIALS; PRECISION FLOATING; RUN TIME; SYSTEM-LEVEL ARCHITECTURES; VECTOR PROCESSING; XILINX VIRTEX;

DIGITAL ARITHMETIC;

EID: 46249105569     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311302     Document Type: Conference Paper

References (6)

1. K. Underwood, "FPGAs vs. CPUs: Trends in Peak Floating-Point Performance," in Proc. of the ACM Symp. on Field-Programmable Gale-Arrays (FPGA). ACM press, pp. 171-180, 2004.
2. IEEE Standard for Binary Floating-Point Arithmetic,IEEE Std. 754-1985.
3. P. Cvitanovic and T. Kinoshita, "Sixth-order radiative corrections to the electron magnetic moment," Phys. Rev. Letters, vol. 29, no. 1534, 1972, see also http://www.npaci.edu/envision/v16.1/kinoshita.html.
4. G. Govindu, R. Scrofano, and V. Pasanna, "A Library of Parameterizable Floating-point Cores for FPGAs and their Application to Scientific Computing." in Proc. of the 2005 Intl. Conf on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2005, pp. 137-148.
5. Xilinx ISE Foundation rel. 7.1, http://www.xilinx.com/
6. Virtex-II Platform FPGAs: Complete Data Sheet, June 2004.