-
1
-
-
46249097714
-
-
3D Packaging: Density, Design, and Decisions, presentation by Jim Walker, Gartner-Dataquest, at the 3D Architectures for Semiconductor Integration and Packaging Conference, June 2005
-
"3D Packaging: Density, Design, and Decisions", presentation by Jim Walker, Gartner-Dataquest, at the 3D Architectures for Semiconductor Integration and Packaging Conference, June 2005
-
-
-
-
2
-
-
27744460412
-
More Life For Moore's Law
-
June 20, P
-
Adam Aston, "More Life For Moore's Law", Business Week June 20,2005, P.74-75
-
(2005)
Business Week
, pp. 74-75
-
-
Aston, A.1
-
4
-
-
34249801921
-
3D System Integration Technologies
-
Eric Beyne, "3D System Integration Technologies", Proceeding HTC 2006, pp. 19-27
-
(2006)
Proceeding HTC
, pp. 19-27
-
-
Beyne, E.1
-
5
-
-
46249088992
-
-
Research Programs in 3D Technology for Circuits, presentation by Daniel J. Radack, DARPA, at the 3D Architectures for Semiconductor Integration and Packaging Conference, June 2005
-
"Research Programs in 3D Technology for Circuits", presentation by Daniel J. Radack, DARPA, at the 3D Architectures for Semiconductor Integration and Packaging Conference, June 2005
-
-
-
-
6
-
-
0034462309
-
System-Level Performance Evaluation of Three-Dimensional Integrated Circuits
-
DECEMBER
-
Arifur Rahman and Rafael Reif, "System-Level Performance Evaluation of Three-Dimensional Integrated Circuits", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 8, NO. 6, DECEMBER 2000, pp.671
-
(2000)
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
, vol.8
, Issue.6
, pp. 671
-
-
Rahman, A.1
Reif, R.2
-
7
-
-
2442653656
-
Interconnect Limits on Gigascale Integration (GSI) in the 21st Century
-
MARCH
-
Jeffrey A. Davis et al., "Interconnect Limits on Gigascale Integration (GSI) in the 21st Century", PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001, pp.305-324
-
(2001)
PROCEEDINGS OF THE IEEE
, vol.89
, Issue.3
, pp. 305-324
-
-
Davis, J.A.1
-
8
-
-
46249124574
-
-
3D Integration: a status report, presentation by Philip Garrou, RTI, at the 3D Architectures for Semiconductor Integration and Packaging Conference, June 2005
-
"3D Integration: a status report", presentation by Philip Garrou, RTI, at the 3D Architectures for Semiconductor Integration and Packaging Conference, June 2005
-
-
-
-
9
-
-
0042612609
-
Hourglass-shaped Conductive Connection Through Semiconductor Structures
-
United States Patent 3,648,131, Mar. 7
-
K. Stuby and W. Falls, "Hourglass-shaped Conductive Connection Through Semiconductor Structures", United States Patent 3,648,131, Mar. 7, 1972
-
(1972)
-
-
Stuby, K.1
Falls, W.2
-
10
-
-
18144413062
-
-
Philip Garrou, Future ICs Go Vertical, Semiconductor International 2/1/2005
-
Philip Garrou, "Future ICs Go Vertical", Semiconductor International 2/1/2005
-
-
-
-
11
-
-
17644378782
-
-
Bryan Black et al., 3D Processing Technology and its Impact on iA32 Microprocessors, Proceedings of ICCD 2004, 11-13 Oct. 2004, Pages:316 - 318 (Intel Corporation)
-
Bryan Black et al., "3D Processing Technology and its Impact on iA32 Microprocessors", Proceedings of ICCD 2004, 11-13 Oct. 2004, Pages:316 - 318 (Intel Corporation)
-
-
-
-
12
-
-
46249097450
-
-
FaStack Technology, presentation by Robert Patti, Tezzaron, at the 3D Architectures for Semiconductor Integration and Packaging Conference, June 2005
-
"FaStack Technology", presentation by Robert Patti, Tezzaron, at the 3D Architectures for Semiconductor Integration and Packaging Conference, June 2005
-
-
-
-
13
-
-
23844447366
-
Wafer-Level 3D Interconnects Via Cu Bonding
-
San Diego, CA, USA, October
-
Patrick Morrow et al., "Wafer-Level 3D Interconnects Via Cu Bonding", in Proceedings of the 21st Advanced Metallization Conference, San Diego, CA, USA, October 2004
-
(2004)
Proceedings of the 21st Advanced Metallization Conference
-
-
Morrow, P.1
-
14
-
-
2942658001
-
Timing, Energy, and Thermal Performance of Three Dimensional Integrated Circuits
-
April 26-28, Boston, Massachusetts, USA
-
Shamik Das et al., "Timing, Energy, and Thermal Performance of Three Dimensional Integrated Circuits", GLSVLSI'04, April 26-28, 2004, Boston, Massachusetts, USA
-
(2004)
GLSVLSI'04
-
-
Das, S.1
-
15
-
-
33745949868
-
Technology, Performance, and Computer Aided Design of Three Dimensional Integrated Circuits
-
Apr
-
Shamik Das et al., "Technology, Performance, and Computer Aided Design of Three Dimensional Integrated Circuits", Proc. ISPD, Apr. 2004
-
(2004)
Proc. ISPD
-
-
Das, S.1
-
17
-
-
46249133358
-
-
Perspectives on 3D-IC Technology, presentation by Albert M. Young, IBM T.J. Watson Research Center, at the 3D Architectures for Semiconductor Integration and Packaging Conference, June 2005
-
"Perspectives on 3D-IC Technology", presentation by Albert M. Young, IBM T.J. Watson Research Center, at the 3D Architectures for Semiconductor Integration and Packaging Conference, June 2005
-
-
-
-
18
-
-
61649116812
-
Assembly Technology for Three-Dimensional (3D) Integrated Circuits (ICs)
-
A.W. Topol et al., "Assembly Technology for Three-Dimensional (3D) Integrated Circuits (ICs)", Proceeding of VMIC 2005
-
(2005)
Proceeding of VMIC
-
-
Topol, A.W.1
-
19
-
-
33845571282
-
A CMOS-compatible process for fabricating electrical through-vias in silicon
-
San Diego, CA, USA, May
-
P.S. Andry et al.; "A CMOS-compatible process for fabricating electrical through-vias in silicon", Proc. 56th Electronic Components and Technology Conf., San Diego, CA, USA, May 2006, p.831-837
-
(2006)
Proc. 56th Electronic Components and Technology Conf
, pp. 831-837
-
-
Andry, P.S.1
-
20
-
-
33845562490
-
System-on-package (SOP) technology, characterization and applications
-
San Diego, CA, USA, May
-
J.U. Knickerbocker et al.; "System-on-package (SOP) technology, characterization and applications", Proc. 56th Electronic Components and Technology Conf, San Diego, CA, USA, May 2006, p.415-421
-
(2006)
Proc. 56th Electronic Components and Technology Conf
, pp. 415-421
-
-
Knickerbocker, J.U.1
-
21
-
-
46249090888
-
-
Ziptronix's press release at 26 September, 2005
-
Ziptronix's press release at 26 September, 2005
-
-
-
-
22
-
-
46249114931
-
-
MIT Lincoln Labortary's 3D Circuit Integration Technology Program, presentation by Craig Keast, MIT Lincoln Labortary, at the 3D Architectures for Semiconductor Integration and Packaging Conference, June 2005
-
"MIT Lincoln Labortary's 3D Circuit Integration Technology Program", presentation by Craig Keast, MIT Lincoln Labortary, at the 3D Architectures for Semiconductor Integration and Packaging Conference, June 2005
-
-
-
-
23
-
-
46249123771
-
-
Samsung's press releases at 13 April, 2006
-
Samsung's press releases at 13 April, 2006
-
-
-
-
24
-
-
39749177820
-
Through Silicon Via and 3-D Wafer/Chip Stacking Technology
-
Kenji Takahashi and Masahiro Sekiguchi, "Through Silicon Via and 3-D Wafer/Chip Stacking Technology", Proceedings of VLSI 2006
-
(2006)
Proceedings of VLSI
-
-
Takahashi, K.1
Sekiguchi, M.2
-
25
-
-
33845569550
-
Low-cost through-hole electrode interconnection for 3D-SiP using room-temperature bonding
-
San Diego, CA, USA, May
-
N. Tanaka and Y. Yoshimura, "Low-cost through-hole electrode interconnection for 3D-SiP using room-temperature bonding", Proc. 56th Electronic Components and Technology Conf, San Diego, CA, USA, May 2006, p.814-818
-
(2006)
Proc. 56th Electronic Components and Technology Conf
, pp. 814-818
-
-
Tanaka, N.1
Yoshimura, Y.2
-
26
-
-
46249098898
-
-
3D Chip-Stacking Technology and Industrial Applications, presentation by K. Takahashi, Toshiba, at the 3D Architectures for Semiconductor Integration and Packaging Conference, June 2005
-
"3D Chip-Stacking Technology and Industrial Applications", presentation by K. Takahashi, Toshiba, at the 3D Architectures for Semiconductor Integration and Packaging Conference, June 2005
-
-
-
-
27
-
-
46249117583
-
-
Different Approaches to 3D Chips, presentation by M. Koyanagi, Tohoku University, at the 3D Architectures for Semiconductor Integration and Packaging Conference, June 2005
-
"Different Approaches to 3D Chips", presentation by M. Koyanagi, Tohoku University, at the 3D Architectures for Semiconductor Integration and Packaging Conference, June 2005
-
-
-
-
28
-
-
33750922540
-
Thermal Analysis of a 3D Die-Stacked High-Performance Microprocessor
-
April 30-May 2, Philadelphia, PA, USA
-
Kiran Puttaswamy and Gabriel H. Loh, "Thermal Analysis of a 3D Die-Stacked High-Performance Microprocessor" GLSVLSI'06, April 30-May 2, 2006, Philadelphia, PA, USA.
-
(2006)
GLSVLSI'06
-
-
Puttaswamy, K.1
Loh, G.H.2
-
29
-
-
28344443452
-
Thermal Via Placement in 3D les
-
April 3-6, San Francisco, California, USA
-
Brent Goplen and Sachin Sapatnekar, "Thermal Via Placement in 3D les" ISPD'05, April 3-6, 2005, San Francisco, California, USA.
-
(2005)
ISPD'05
-
-
Goplen, B.1
Sapatnekar, S.2
|