Low-cost through-hole electrode interconnection for 3D-SiP using room-temperature bonding

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 814-818

  Tanaka, Naotaka ^a   Yoshimura, Yasuhiro ^a   Naito, Takahiro ^b   Miyazaki, Chuichi ^b   Uematsu, Toshihide ^b   Hanada, Kenji ^b   Toma, Norihisa ^b   Akazawa, Takashi ^b  

^a HITACHI LTD   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRODES; MULTILAYERS; PRINTED CIRCUIT BOARDS; RANDOM ACCESS STORAGE; THIN FILM CIRCUITS;

INTERPOSER; MECHANICAL CAULKING; PACKAGE THICKNESS; STABLE MASS PRODUCTION PROCESS;

INTERCONNECTION NETWORKS;

EID: 33845569550     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645751     Document Type: Conference Paper

References (6)

1. K. Koyanagi, "Future System-on-Silicon LSI Chip", IEEE Micro, Vol. 18, No. 4, 1988, pp. 17-22.
2. th Ann. Int. KGD Packaging and Test Workshop, 2000, pp. 336-352.
3. th Electronic Components and Technology Conf, 2000, pp. 702-705.
4. Y. Sogawa, T. Yamazaki, I. Hazeyama and S. Kitajo, "Reliability of an Ultra-high-density 3-dimensional-stacked Package "FFCSP"", Proc. of International Conference on Electronics Packaging, Japan, Apr. 2004, pp. 41-46.
5. K. Hara, "The Optimazation of Terminal Structure for Interconnecting in 3D Packaging Technology with Through-silicon Vias", Proc. of International Conference on Electronics Packaging, Japan, Apr. 2005
6. th Electronic Components and Technology Conf, 2005, pp. 788-794.