Defect-tolerant CMOL cell assignment via satisfiability

IEEE Sensors Journal

Volumn 8, Issue 6, 2008, Pages 823-830

  Hung, William N N ^a,b,c   Gao, Changjian ^d   Song, Xiaoyu ^a,d   Hammerstrom, Dan ^a,d  

^a IEEE

^b PORTLAND STATE UNIVERSITY   (United States)

^c SYNOPSYS INC   (United States)

^d Department of Electrical and Computer Engineering   (United States)

Author keywords

Field programmable gate array (FPGA); Nanodevice; Reconfigurable computing

Indexed keywords

BOOLEAN ALGEBRA; BOOLEAN FUNCTIONS; MAPS; MECHANICS; TELECOMMUNICATION NETWORKS;

(I ,J) CONDITIONS; BOOLEAN CONSTRAINTS; CELL ASSIGNMENT; CELL ASSIGNMENT PROBLEM; CIRCUIT ARCHITECTURES; CMOL ARCHITECTURE; DEFECT MODELING; NOR GATES; SATISFIABILITY (QSAT); TIMING DELAYS;

DEFECTS;

EID: 44649103871     PISSN: 1530437X     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSEN.2008.923261     Document Type: Article

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