Board-level multiterminal net assignment for the partial cross-bar architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 3, 2003, Pages 511-513

  Song, Xiaoyu ^a   Hung, William N N ^a   Mishchenko, Alan ^b   Chrzanowska Jeske, Malgorzata ^a   Kennings, Andrew ^a   Coppola, Alan ^c  

^a Portland State University   (United States)

^b UNIVERSITY OF WATERLOO   (Canada)

^c CYPRESS SEMICONDUCTOR   (United States)

Author keywords

Digital design; Layout; Logic emulation; Satisfiability; Very large scale integration (VLSI)

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTATIONAL COMPLEXITY; FIELD PROGRAMMABLE GATE ARRAYS; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

BOARD LEVEL MULTITERMINAL NET ASSIGNMENT; DIGITAL DESIGN; LOGIC EMULATION; PARTIAL CROSS BAR ARCHITECTURE; SATISFIABILITY BASED METHOD;

INTEGRATED CIRCUIT LAYOUT;

EID: 0041919447     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.812322     Document Type: Article

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