Design of k-WTA/sorting network using maskable WTA/MAX circuit

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2001, Pages 69-72

  Lin, C S ^a   Ou, S H ^a   Liu, B D ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; FUZZY SETS; INTERCONNECTION NETWORKS; MASKS; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

WINNER-TAKE-ALL (WTA) CIRCUITS;

NEURAL NETWORKS;

EID: 0034842637     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A high-precision current-mode WTA-MAX circuit with multichip capability
2. Analysis for a class of winner-take-all model
3. A parallel bit-level maximum/minimum selector for digital and video signal processing
4. Efficient VLSI architecture for columnsort