A 2.5-GHz DDFS-PLL with 1.8-MHz bandwidth in 0.35-μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 6, 2008, Pages 1403-1413

  Bonfanti, Andrea ^a,b   De Caro, Davide ^a,c   Grasso, Alfio Dario ^a,d   Pennisi, Salvatore ^a,d   Samori, Carlo ^a,b   Strollo, Antonio G M ^a,c  

^a IEEE

^b POLITECNICO DI MILANO   (Italy)

^c UNIVERSITY OF NAPLES FEDERICO II   (Italy)

^d UNIVERSITY OF CATANIA   (Italy)

Author keywords

Bluetooth transmitter; CMOS integrated circuits; Digital arithmetic; Frequency synthesizers; Phase noise; Phase locked loop (PLL); Signal synthesis; Voltage controlled oscillator (VCO)

Indexed keywords

BANDWIDTH; CELLULAR TELEPHONE SYSTEMS; CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; ELECTRIC CURRENTS; FREQUENCY SYNTHESIZERS; MICROFLUIDICS; MODULATION; PHASE LOCKED LOOPS; PHASE NOISE; SIGNAL GENERATORS; SPECIFICATIONS; TECHNOLOGY; TELECOMMUNICATION SYSTEMS;

CMOS TECHNOLOGIES; DELTA-SIGMA; DIRECT DIGITAL FREQUENCY SYNTHESIZER (DDFS); FRACTIONAL N; FREQUENCY RESOLUTIONS; LOOP BAND WIDTH; OFFSET PLL; OUTPUT FREQUENCIES; POWER DISSIPATIONS; RMS PHASE; SETTLING TIME; SYNTHESIZER ARCHITECTURE; WIDE BAND FREQUENCIES;

MODULATORS;

EID: 44649083087     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.922721     Document Type: Article

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